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CS7654
CCD Color-Space Processor with Analog Output
Features
l ITU-601
Description
The CS7654 is a low-power Digital Color-Space Processor for CCD cameras. It provides all the necessary digital image processing for standard four-color interline transfer CCD imagers. The CS7654 processes the magenta, yellow, cyan, and green (MYCG) CCD imager data into YCrCb formatted component digital video and into analog PAL or NTSC. Internal processing includes color separation, automatic white balance, user programmable gamma correction, programmable scaling (interpolation), digital output formatting and encoding function for analog output. Also, a special "Chroma Kill" circuit eliminates false colors during saturation. Video output can be formatted to be compatible with NTSC-M, NTSC-J, PAL-B,D,G,H,I,M,N, and Combination N systems. Closed Caption is supported in NTSC. Three 10bit DACs provide two channels for an S-Video output port and one composite video outputs.A High-speed I2C compatible control interface is provided for in system design. A general purpose I/O port is also available to help conserve valuable board space and to provide up to eight "boot" configurations.The CS7654 is designed to work directly with the CS7615 CCD Imager Analog Processor.
Compliant Image Formatting l ITU-656 and SMPTE-125/M Transports l I2C Control Interface l Limited Secondary I2C Bus Master l Automatic White Balance l Programmable Gamma Correction l Programmable Interpolation l Programmable Luma Gain and Saturation Control l Fully Programmable Color Separation Matrix Coefficients l Supports up to 1440, active pixels per line, with no limitation on Vertical Size l Programmable "Chroma Kill" circuit l Highly integrated for low part count cameras l Three DACs providing simultaneous composite, S-video outputs l Multi-standard support for NTSC-M, NTSCJAPAN, PAL (B, D, G, H, I, M, N, Combination N) l On-chip voltage reference generator modes, tristate DACs and power down mode.
ORDERING INFORMATION CS7654-KQ 0 to 70 C (10 mm x 10 mm x 1.4 mm)I
64-pin TQFP
CCD MOSAIC DATA
DEFORMATTER
COLOR SEPARATION AND ANITALIASING
WHITE BALANCE
AWB CONTROL
INTERPOLATION AND FILTER CHROMA
10-BIT DAC 10-BIT DAC 10-BIT DAC
CHROMA
GAMMA CORRECTION
SCALER
OUTPUT FORMATTER
VIDEO FORMATTER LUMA INTERPOLATION AND DELAY
COMPOSITE
LUMA VREF/ VSYNC HREF/ HSYNC
SECONDARY I2C BUS
I2C INTERFACE
REGISTER BLOCK
PLL AND CLOCK DRIVER
EXTERNAL TIMING
PRIMARY I2C BUS XTAL
Preliminary Product Information
Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved)
MAY `99 DS330PP2 1
CS7654
TABLE OF CONTENTS
CHARACTERISTICS/SPECIFICATIONS ............................................................ 4 DIGITAL CHARACTERISTICS.................................................................... 4 SWITCHING CHARACTERISTICS ............................................................. 4 POWER CONSUMPTION ........................................................................... 5 POWER CONSUMPTION ........................................................................... 6 CONTROL PORT CHARACTERISTICS ..................................................... 6 RECOMMENDED OPERATING CHARACTERISTICS............................... 7 ABSOLUTE MAXIMUM RATINGS .............................................................. 7 GENERAL DESCRIPTION .................................................................................. 8 Overview ..................................................................................................... 8 Digital Output Formats .............................................................................. 11 Internal Horizontal Scaler ......................................................................... 11 CLKIN2X Input Timing .............................................................................. 12 CLKOUT_GRG ......................................................................................... 12 INTERN.AL PROCESSING ............................................................................... 13 Input Data Format and Chroma Separator ............................................... 13 White Balance and Gamma Correction .................................................... 13 Chroma Kill ............................................................................................... 13 Internal Filters ........................................................................................... 14 Analog Video Timing Generator ............................................................... 14 Color Subcarrier Synthesizer .................................................................... 14 Chroma Path ............................................................................................. 14 Luma Path ................................................................................................ 14 Digital to Analog Converters ..................................................................... 15 Voltage Reference .................................................................................... 15 Current Reference .................................................................................... 15 Closed Caption Insertion .......................................................................... 15 Control Registers ...................................................................................... 16 Testability .................................................................................................. 16 OPERATIONAL DESCRIPTION ........................................................................ 16 Reset Hierarchy ........................................................................................ 16 Vertical Timing ................................................................................... 16 NTSC Interlaced ................................................................................. 17 PAL Interlaced .................................................................................... 18 Progressive Scan ............................................................................... 18 Digital Video Input Modes ......................................................................... 18 Multi-standard Output Format Modes ....................................................... 20 Subcarrier Generation .............................................................................. 20 Color Bar Generator ................................................................................. 20 Super White/Super Black support ............................................................. 21 FILTER RESPONSES ................................................................................ 23
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advanced product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
CS7654
INTERNAL REGISTER STRUCTURE AND USER INTERFACE ..................... 25 Operating CS7654 in Normal I2C Configuration (Three-Byte Mode) ....... 25 Station Address .................................................................................. 25 Write Operations in Three-Byte Mode ............................................... 25 Address Set Operation ....................................................................... 26 Read Operations in Three-Byte Mode ............................................... 26 Operating CS7654 in Four-Byte I2C Configuration ............................ 26 Write Operations in Four-Byte mode ................................................. 26 Read Operations in Four-Byte Mode ................................................. 27 Initializing Slave Devices on Secondary I2C bus from an EPROM .......... 27 Controlling the Configuration Process ...................................................... 28 Reserved Registers and Test Pins ........................................................... 29 General Purpose I/O Port ......................................................................... 29 ANALOG ............................................................................................................ 30 Analog Timing .......................................................................................... 30 VREF ........................................................................................................ 30 ISET-DAC ................................................................................................. 30 DACs ........................................................................................................ 30 Luminance DAC ................................................................................. 30 Chrominance DAC ............................................................................. 31 COMP_VID DAC ................................................................................ 31 REGISTER DESCRIPTION ............................................................................... 32 BOARD DESIGN AND LAYOUT CONSIDERATIONS ..................................... 53 Power and Ground Planes ....................................................................... 53 Power Supply Decoupling ........................................................................ 53 Digital Interconnect ................................................................................... 53 Analog Interconnect ................................................................................. 53 Analog Output Protection ......................................................................... 54 ESD and Latch up Protection ................................................................... 54 External DAC Output Filter ....................................................................... 54 PIN DESCRIPTIONS ......................................................................................... 55 PACKAGE DIMENSIONS ................................................................................. 60
3
CS7654
CHARACTERISTICS/SPECIFICATIONS
DIGITAL CHARACTERISTICS (TA = 25 C; VDD = 5 V; CL = 30 pF; Input Levels:
1 = VDD.) Parameter Symbol VIH VIL IIN CDI Min VDD - 0.8 VOH VOL IZ VDD - 0.4 0.4 Typ 10 -0.7 -
logic 0 = 0 V, logic Max 0.8 10.0 10.0 Unit V V A pF V V V A
Logic Inputs High-Level Input Voltage
Low-Level Input Voltage Input Leakage Current Input Pin Capacitance Input Clamp Voltage
Logic Outputs High-Level Output Source Current @ IOH = 1mA
Low-Level Output Sink Current @ IOL = 1mA High-Z Leakage Current
SWITCHING CHARACTERISTICS (TA = 25 C; VDD = 5 V; CL = 30 pF; Input Levels:
logic 1 = VDD.) Parameter Digital Input CLKIN2X Frequency Range Input Data setup time, DI[9:0] Input Data hold time, DI[9:0] Symbol fCLK2X tS1 tH1 Interleaved Data fCLKOUT_GRG tOH tPD tR tF Min 5 5 Typ 27 0 1.9 15 15
logic 0 = 0 V, Unit MHz ns ns MHz ns ns ns ns
Max 30 30 5 -
Digital Output Channel A/B Digital Data Output Clock
Channel A/B Output Hold Time Channel A/B Output Propagation Delay Digital Output Rise Time with 30 pF load Digital Output Fall Time with 30 pF load
.
Specifications are subject to change without notice
4
CS7654
CLKIN2X tH2 tS2 CLKIN tS1 tH1 Mosaic Input Data DI[9:0]
Input Timing Diagram
CLKOUT tPD Output Data DOA[9:0] DOB[9:0] tOH
Output Timing Diagram
POWER CONSUMPTION (TA = 25 C; VDD = 5 V; CL = no load; Input Levels:
Parameter Power Supply Supply Voltage Digital Supply Current (Encoder) Analog Supply (Encoder) Low-Z Power Supply Rejection Ratio Normal Mode Low Power Mode Symbol VAA IAA1 (Note 1) IAA2 PSRR IDD IDD (Notes 2, 3) (Notes 2, 4) (Notes 2, 3) (Notes 2, 4) IO IO IB IB MAT VOC ROUT COUT ODEL (Note 5) TRF Min 4.75 32.9 8.22 32.2 8.04 0 -
logic 0 = 0 V, logic 1 = VDD.) Typ 5.0 70 100 0.02 150 7 34.7 8.68 33.9 8.48 2 15 4 2.5 0.05 200 16 36.5 9.13 35.7 8.92 + 1.4 30 12 5 Max 5.25 Unit V mA mA %/% mA mA mA mA mA mA % V k pF nsec nsec
Analog Outputs Full Scale Output Current COMP_VID/Y/C Full Scale Output Current COMP_VID/Y/C LSB Current COMP_VID/Y/C LSB Current COMP_VID/Y/C DAC-to DAC Matching Output Compliance Output Impedance Output Capacitance DAC Output Delay DAC Rise/Fall Time
Notes: 1. Low-Z - 3 dacs on
2. Output current levels with ISET = 4 K , VREF = 1.232 V. 3. DACs are set to low impedance mode 4. DACs are set to high impedance mode 5. Times for black-to-white-level and white-to-black-level transitions.
5
CS7654
POWER CONSUMPTION (Continued)
Parameter Symbol VOV UVC Min 1.170 DNL INL DG DP HA SNR SAT -1 -2 70 Typ 1.232 + 0.5 +1 2 + 0. 5 1 Max 1.294 10 10 +1 +2 5 +2 2 2 Units V uA Bits LSB LSB % deg deg dB %
Voltage Reference Reference Voltage Output Rreference Input Current Static Performance DAC Resolution Differential Non-Linearity Integral Non-Linearity Dynamic Performance Differential Gain Differential Phase Hue Accuracy Signal to Noise Ratio Saturation Accuracy
CONTROL PORT CHARACTERISTICS (TA = 25 C; VDD = 5 V; Input Levels:
1 = VDD.) Parameter SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Pulse Width Setup Time for Repeat Start Condition SDAIN Hold Time from SCL Falling SDAIN Setup Time from SCL Rising SDAIN and SCL Rise Time SDAIN and SCL Fall Time Setup Time for Stop Condition High Low Symbol fSCL tbuf thdst thigh tlow tsust thdd tsud tr tf tsusp
Repeated Start
logic 0 = 0 V, logic Max 400 1.0 0.3 Unit kHz s s s s s s s s s s
Min 1.3 0.6 0.6 1.3 0.6 0 0.1 0.6
Stop SD A t SCL
Start
Stop
buf
t
hdst
t high
t hdst
tf
t
susp
t
low
t
hdd
2
t
sud
t
sust
t
r
I C Timing Diagram
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CS7654
RECOMMENDED OPERATING CHARACTERISTICS
Parameter Power Supply Voltage Ground to Ground Voltage Differential Digital Input Rise/Fall Time CLKIN Level Setup to CLKIN2X Rising (non-interpolated) CLKIN Level Hold after CLKIN2X Rising (non-interpolated) Digital Input Voltage Range Operating Temperature Range TA tS2 tH2 Symbol VDD Min 4.5 8 8 0 0 Typ 5.0 Max 5.5 10 10 VDD 70 Unit V mV ns ns ns V C
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Digital Input Voltage Range Forced Digital Output Current Sustained Digital Output Voltage Output Short Circuit Current Operating Temperature Range Lead Solder Temperature (10 s duration) Storage Temperature Range TA Symbol VDD Min -0.3 GND - 0.3 GND - 0.3 0 -65 Max 6.0 VDD + 0.3 50 VDD + 0.3 70 +260 +160 Unit V V mA V mA C C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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CS7654
GENERAL DESCRIPTION Overview
The CS7654 is a complete color space converter and multi-standard digital video encoder implemented in current CMOS technology. It provides all necessary digital image processing for standard four-color interline transfer CCD imagers. The CS7654 processes the magenta, yellow, cyan, and green (MYCG) CCD imager data into YCrCb formatted component and into NTSC-M, NTSC-J, PAL-B, PAL-D, PAL-G, PAL-H, PAL-I, PAL-M, PAL-N, or PAL-N Argentina-compatible analog video. Two 10-bit DAC outputs provide high quality SVideo analog output while another 10-bit DAC simultaneously generates composite analog video. In order to lower overall system costs, the CS7654 provides an internal voltage reference that eliminates the requirement for an external, discrete, three-pin voltage reference. The CS7654 forms the heart of a four chip digital CCD Camera. The four chips include the CCD imager, the CS7615 CCD digitizer, the CS7654 color space processor, and a vertical drive interface-chip for the CCD imager. Most four-phase CCD imagers (and their associated vertical drives) can be used with the CS7615 digitizer and the CS7654 processor to form a simple and cost-effective Analog output format digital camera. The CS7615 and CS7654 together support imager formats ranging from 175x175 pixels up to 1000x1000 pixels. Timing control is located in the CS7615 analog processor, while the CS7654 synchronizes itself by decoding the timing cues embedded in the CS7615 data stream. Alternately, the CS7654 accepts horizontal and vertical timing signals on HREFIN and VREFIN pins. The block diagram in Figure 1 illustrates a typical system interconnect. The CS7654 provides color separation of standard MYCG chroma block data from industry standard
8
6 CCD
CS7615
CDS/ADC
CS7654
Image Processor I2 C
512x480
Timing Vertical Drive
I 2C
6 CCD Bias
2 +5V
+18V to +12V
Figure 1. Typical 4-Chip Digital CCD Camera
four-color CCD imagers. Gamma correction and white balance adjustment functions are also included in the CS7654. The YCrCb (luminance and chrominance) data is output at twice the scaled pixel rate in 10-bit format. The digital YCrCb output data from the CS7654 conforms to the ITU-656 parallel component digital video recommendation with embedded synchronization (see Embedded EAV and SAV discussion). The CS7654 incorporates an internal horizontal scaler which may be turned on to increase the horizontal pixel count of the popular 360 (CIF) and 512 horizontal pixel per line imagers. The most common target resolutions for the scaler are 640 and 720 pixels per line (square and rectangular pixel formats), but it is possible to provide generic scaling of M/N where M and N are values from 1 to 31. The CS7615 and CS7654 chip set supports a wide range of imager formats while providing an output format that follows the ITU-601 Component Digital Video recommendation. The ITU-601 document primarily specifies horizontal resolutions of 720 active horizontal pixels (which is required for broadcast television compatibility). However, many of today's digital video receivers are capable of operating with a wide range of video image formats. Even though these digital video receivers allow image formats not specified in the ITU601/656 recommendation, all of these receivers expect the basic ITU-601/656 protocol to be followed in terms of data sequence and timing cues. This is the case with the CS7654, where all output formats
CS7654
follow the ITU-601/656 recommendation even if the image formats differ in horizontal and vertical pixel dimensions. .
EAV H=1 Lines 1 to 19 V=1
SAV H=0 Vertical Blanking
Horizontal Blanking
Lines 20 to 263 V=0
Active Video Field 1
F=0 Lines 4 to 265
Lines 264 to 282 V=1
Vertical Blanking
Horizontal Blanking
Lines 283 to 525 V=0
Active Video Field 2
F=1 Lines 266 to 3
640
779
Figure 2. Horizontal and Vertical Timing States (640x480 resolution)
639
0
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CS7654
Word 1280 1281 1282 1283 1284 1285 1286 1287
Data Content 1111 0000 0000 1FV1 1000 0001 1000 0001 1111 0000 0000 P3P2P1P0 0000 0000 0000 0000
Pixel 640
Notes EAV EAV EAV EAV For pixels 642 to 777 Cr = Cb = 80h Y = 10h
641 642
643
1552 1553 1554 1555 1556 1557 1558 1559 0 1 2 3 4 5 6 7 2n 2n + 1 2n + 3 1272 1273 1274 1275 1276 1277 1278 1279
1000 0001 1000 0001 1111 0000 0000 1FV0
0000 0000 0000 0000 1111 0000 0000 P3P2P1P0 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cbn Yn Crn Yn+1 Cb636 Y636 Cr636 Y637 Cb638 Y638 Cr638 Y639
776
777 778
779 0
1 2
SAV SAV SAV SAV Start of Digital Video For VBLANK line 1 to 19 and 264 to 283 Cr = Cb = 80h Y = 10h
3 n
n+1 636
For active pixels 20 through 263 and 283 to 525 for n=even from pixels 0 to 638
637 638
End of Digital VIdeo
Table 1. Detail of Scan Line for 640x480 Image
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CS7654
Digital Output Formats
The CS7654 can output data in a 10-bit format at a 2x output pixel clock rate. Figure 3 details the clock and data relationships. The output data transitions on the falling edge of the clock such that the rising edge of the clock can be used to latch the data into subsequent circuitry. The CS7654 delivers 4:2:2 component digital video output data in YCrCb format. The data conforms to the ITU-R BT.656 specification. The Y component range is 16-235 (8-bit data) and the Cr and Cb component ranges are 16-240 (8-bit data). However, by setting CLIP_OFF (register 07h bit 6 at SA34h) to a value of 1, the output data can be extended to a range of 1-254 (8-bit data). Only 00 and FF are restricted to allow digital timing codes. The CLIP_OFF register will set the digital section on the data path to the extended range of value. If you want to have the analog output set to extended range, you will also have to set Register 06h at Station Address (SA ) 0x00. The digital outputs are configured for 10-bit interleaved Y and CrCb data
24.5454MHz CLKOUT SAV DOA [9-0] Line 3 Pixel 776 to Line 4 Pixel 3 80h 10h 80h 10h FFh 00h 00h ABh 80h 10h 80h 10h 80h 10h
The CS7654 supports both 8-bit and 10-bit operation as per the ITU-656 recommendation. The ITU656 recommendation defines the primary data path as 8-bits wide with two additional fractional bits that can be used to form a 10-bit data path. If only 8-bits of output data are used, the two LSBs, DOUT1 and DOUT0 are not used. However, DOUT[9:2] is connected exactly the same as in a 10-bit system. This is essential to properly pass the image data and synchronization signals to the next component.
Internal Horizontal Scaler
The internal horizontal scaler is used to bridge between common CCD imager formats and computer or television formats. Several pre-defined scaler modes may be selected by writing a 3-bit value to bits 0-2 of register 04h at SA 0x34h. These default scaling modes are described in Table 2. If the CUSTOM bit (bit 3 of register 04h at SA 0x34h) is set to a 1, then the scaling ratio is determined by the M and N values contained in the Scaler Control registers (2Dh - 2Fh at SA 0x34h.)
EAV DOA [9-0] Line 263 Pixel 638 to Line 264 Pixel 645 80h 10h 80h 10h FFh 00h 00h F1h 80h 10h 80h 10h 80h 10h
EAV DOA [9-0] Line 525 Pixel 638 to Line 1 Pixel 645 Cb638 Y638 Cr638 Y639 FFh 00h 00h 9Dh 80h 10h 80h 10h 80h 10h
NOTE: EAV, SAV, and Blanking data values are based on the 8 MSB's of the output data, the two LSBs are considered fractional.
Figure 3. 2x Pixel Clock, 10-Bit interleaved Output Format for 640x480 Image Format.
11
CS7654
CLKIN2X Input Timing
The CLKIN2X, pin 59, will always require a primary pixel rate clock source. CCD manufacturers generally specify a pixel clock frequency that is compatible with one of the analog encoders that can be used with a given imager. If the analog output is used, the clock frequency input must be matched precisely. However, digital display systems, such as those based on VGA graphics adapter cards and Zoom Video systems, are generally not sensitive to pixel clock frequency, and will tolerate a wide range of pixel and frame rates.
Mode 000 001 010 011 100 101 110 111 CCD Format CCD 512x480 512x480 512x576 362x480 362x480 362x576 512x576 512x480 512x576 CCD Clock (MHz) 1/2 input clock 9.818 9.346 9.281 6.75 6.75 6.75 9.563 9.000 9.000
Specific pixel-rate clock frequencies for analog encoders include 14.31818 MHz for 768H imagers, the primary ITU-601 13.5 MHz for 720H imagers, and down to 12.272727 MHz clock rates for 640H VGA format imagers.
CLKOUT_GRG
CLKOUT_GRG follows the output data rate The clock output is at 2x the output luma sample rate, there is no non-interlaced digital output on the CS7654.
Output Format same as CCD 640x480 720x480 720x480 640x480 720x480 720x576 720x576 720x480 720x576
Input Clock (MHz) (30 MHz max.) 24.5454 27.000 27.000 24.5454 27.000 27.000 27.000 27.000 27.000
Scaling Ratio 1:1 4:5 9:13 11:16 11:20 1:2 17:24 2:3
Table 2. Default Scaling Modes (Register 04h at SA34h)
12
CS7654
INTERNAL PROCESSING
The internal operation of the CS7654 can be separated into several distinct blocks. The following section provides an overview of how these blocks operate and interact. tains the CS7654 gamma table register address (0Ch), the third byte determines which gamma RAM to update (red, green, and blue), the next 256 bytes contain the gamma table entries. The blue gamma RAM is selected by setting register 0Ch bit 0 to a one; the green gamma RAM is selected by setting register 0Ch bit 1 to a one; and the red gamma RAM is selected by setting register 0Ch bit 2 to a one. Any, or all of the gamma RAMs may be selected . The most common implementation is to write the same gamma table to all 3 RAMs by setting bits 0-2 high. The gamma table itself is loaded from low to high. The first byte after the RAM selection byte will correspond to the value used when the input data is 00h, the 256th byte after the RAM selection byte will correspond to the value used when the input data is FFh. The gamma table is read in a similar manner. However, certain restrictions are made to reads. First, the gamma RAMs may only be read one at a time (RAM selection byte = 01,02,04 only) and, second, the gamma table may only be read when gamma correction is disabled (register 05 bit2 = 0).
Input Data Format and Chroma Separator
The CS7654 accepts up to 10-bit MYCG image data from a CCD digitizer such as the CS7615. The CS7654 internally converts the four-color CCD MYCG interlaced image data into the various color space formats. These include RGB and YUV, as well as YCrCb. The individual image adjustments are performed in the most appropriate color space representation. Ultimately the image is converted to YCrCb format for outputting digital data. The same digital output data is also encoded in the digital video encoder post processor section and converted to analog NTSC or PAL.
White Balance and Gamma Correction
The red and blue color balances can be adjusted through the I2C control port. During the AWB (automatic white balance) sequence the red level is adjusted to minimize the (Y-R) difference component; similarly the blue level is adjusted to minimize the (Y-B) color difference component. An automatic white balance is initiated by writing a 1 to register 05h bit 1 at SA 0x34h. For manual control, the red balance is accessed through register 08h, and the blue balance is accessed through register 09h ( both at SA 0x34h). Gamma correction is provided to offset the non-linear illumination profile of the display device. Separate 256 entry tables are supplied for red, green, and blue. Each entry is 8-bits. The gamma table is programmed through register 0Ch at SA 0x34h. The write format is similar to the write format described in the normal I2C operation section later in this document. The first byte contains the CS7654 device address and write bit, the second byte con-
Chroma Kill
As the brightness of an image increases, the green, yellow, cyan, and magenta pixels within the CCD array will saturate at different intensity levels. As a result, a highly illuminated object or light source may start to look cyan. To overcome this effect, an internal Chroma kill circuit compares the luma and chroma values of each pixel to a set of programmable thresholds. If the pixel's luma value is greater than the Y_THR value (register 27h at SA 0x34h ) and its Cr and Cb values are between the CR_THR_H , CR_THR_L , CB_THR_H, and CB_THR_L threshold values respectively, then that pixel will lose its chroma value (become white.) These thresholds are stored in registers 27h - 2Ch at SA 0x34h.
13
CS7654
Internal Filters
The CS7654 has an internal low-pass chroma filter to reduce the effects of color aliasing. This filter is enabled by writing a value of 0 to bit 4 of register 01h at SA 0x00h. The CS7654 also contains a luma peaking filter to enhance the edges of blurred images. This filter is enabled by setting register 05h bit 3 to a value of 0 at SA 0x34h. By default the lowpass chrome filter is off and the peaking filter is on. The chroma output of the Video Input Formatter is directed to a chroma low-pass 19-tap FIR filter. The filter bandwidth is selected (or the filter can be bypassed) via the CONTROL_1 Register. The passband of the filter is either 650 KHz or 1.3 MHz and the passband ripple is less than or equal to 0.05 dB. The stopband for the 1.3 MHz selection begins at 3 MHz with an attenuation of greater than 35 dB. The stopband for the 650 KHz selection begins around 1.1 MHz with an attenuation of greater than 20 dB. The output of the chroma low-pass filter is connected to the chroma interpolation filter in which upsampling from 4:2:2 to 4:4:4 is accomplished. Following the interpolation filter, the U and V chroma signals pass through two independent variable gain amplifiers in which the chroma amplitude can be varied via the U_AMP and V_AMP 8-bit host addressable registers. The U and V chroma signals are fed to a quadrature modulator in which they are combined with the output from the subcarrier synthesizer to produce the proper modulated chrominance signal. The chroma then is interpolated by a factor of two in order to operate the output DACs at twice the pixel rate. The interpolated filters enable running the DACs at twice the pixel rate and this helps reduce the sinx/x roll-off for higher frequencies and reduces the complexity of the external analog low pass filters.
Analog Video Timing Generator
All timing generation is accomplished via a 27 MHz input applied to the CLKIN2X pin. The Video Timing Generator is responsible for orchestrating most of the other modules in the device. It automatically disables color burst on appropriate scan lines and automatically generates serration and equalization pulses on appropriate scan lines.
Color Subcarrier Synthesizer
The subcarrier synthesizer is a digital frequency synthesizer that produces the appropriate subcarrier frequency for NTSC or PAL. The CS7654 generates the color burst frequency based on the CLK input (27 MHz). Color burst accuracy and stability are limited by the accuracy of the 27 MHz input. If the frequency varies, then the color burst frequency will also vary accordingly. Controls are provided for phase adjustment of the burst to permit color adjustment and phase compensation. Chroma hue control is provided by the CS7654 via a 10-bit Hue Control Register (HUE_LSB and H_MSB). Burst amplitude control is also made available to the host via the 8-bit burst amplitude register (SC_AMP). Horizontal sync to color burst phase adjust is possible by programming the SCH register (register 17h, SA 00h).
Luma Path
Along with the chroma output path, the CS7654 Video Input Formatter initiates a parallel luma data path by directing the luma data to a digital delay line. The delay line is built as a digital FIFO in which the depth of the FIFO replicates the clock period delay associated with the more complex chroma path. Brightness adjustment is also provided via the 8-bit BRIGHTNESS_OFFSET Register.
Chroma Path
The Video Input Formatter delivers 4:2:2 YUV outputs into separate chroma and luma data paths. The chroma path will be discussed here.
14
CS7654
Following the luma delay, the data is passed through an interpolation filter that has a programmable bandwidth, followed by a variable gain amplifier in which the luma dc values are modifiable via the Y_AMP Register. The output of the luma amplifier connects to the sync insertion block. Sync insertion is accomplished by multiplexing, into the luma data path, the different sync dc values at the appropriate times. The digital sync generator takes horizontal sync and vertical sync timing signals and generates the appropriate composite sync timing (including vertical equalization and serration pulses), blanking information, and burst flag. The sync edge rates conform to RS-170A or ITU R.BT601 and ITU R.BT470 specifications. It is also possible to delay the luminance signal, with respect to the chrominance signal, by up to three pixel clocks. This variable delay is useful to offset different propagation delays of the luma baseband and modulated chroma signals. This adjustable luma delay is available only on the COMP_VID output.
Voltage Reference
The CS7654 is equipped with an on-board voltage reference generator (1.232 V) that is used by the DACs. The internal reference voltage is accurate enough to guarantee a maximum of 3% overall gain error on the analog outputs. However, it is possible to override the internal reference voltage by applying an external voltage source to the VREF pin.
Current Reference
The DAC output current-per-bit is derived in the current reference block. The current step is specified by the size of resistor placed between the ISET_DAC current reference pin and electrical ground. A 4 k resistor needs to be connected between ISET_DAC pin and GND. The DAC output currents are optimized to either drive a doubly terminated load of 75 (low impedence mode) or a double terminated load of 300 (high impedence mode). The 2 output current modes are software selectable through a register bit. Note that there are two ISET pins on the device, one for the DACS, and one for the PLL.
Digital to Analog Converters
The CS7654 provides three discrete 27 MHz DACs for analog video. The default configuration is one 10-bit DAC for S-video chrominance, one 10-bit DAC for S-Video luminance, one 10-bit DAC for composite output. All three DACs are designed for driving either low-impedance loads (double terminated 75 ) or high-impedance loads (double terminated 300 ). The DACs can be put into tri-state mode via hostaddressable control register bits. Each of the six DACs has its own associated DAC enable bit. In the Disable Mode, the 10-bit DACs source (or sink) zero current. For lower power standby scenarios, the CS7654 also provides power shut-off control for the DACs. Each DAC has an associated DAC shut-off bit.
Closed Caption Insertion
The CS7654 is capable of NTSC Closed Caption insertion on lines 21 and 284 independently. Closed captioning is enabled for either one or both lines via the CC_EN [1:0] Register bits and the data to be inserted is also written into the four Closed Caption Data registers. The CS7654, when enabled, automatically generates the seven cycles of clock run-in (32 times the line rate), start bit insertion (001), and finally insertion of the two data bytes per line. Data low at the video outputs corresponds to 0 IRE and data high corresponds to 50 IRE. There are two independent 8-bit registers per line (CC_21_1 & CC_21_2 for line 21 and CC_284_1 & CC_284_2 for line 284). Interrupts are also provided to simplify the handshake between the driver
15
CS7654
software and the device. Typically the host would write all 4 bytes to be inserted into the registers and then enable closed caption insertion and interrupts. As the closed caption interrupts occur the host software would respond by writing the next two bytes to be inserted to the correct control registers and then clear the interrupt and wait for the next field. While the RESET pin is held low, the host interface in the CS7654 is disabled and will not respond to host-initiated bus cycles. All outputs are valid after a time period following RESET pin low. A device RESET initializes the CS7654 internal registers to their default values as described by Table 13 and 14, Control Registers. In the default state, the CS7654 video DACs are disabled and the device is internally configured to provide blue field video data to the DACs (any input data present on the V [7:0] pins is ignored at this time). Otherwise, the CS7654 registers are configured for NTSC-M ITU R.BT601 output operation. At a minimum, the DAC Registers 0x04 and 0x05 at Station Address 0x00 must be written (to enable the DACs) and the IN_MODE bit of the CONTROL_0 SA 0x00, Register (0x00) must be set (to enable ITU R.BT601 data input on V [7:0]) for the CS7654 to become operational after RESET.
Control Registers
The control and configuration of the CS7654 is accomplished primarily through the control register block. All of the control registers are uniquely addressable via the internal address register. The control register bits are initialized during device RESET. See the Programming section of this data sheet for the individual register bit allocations, bit operational descriptions, and initialization states. The registers of the CS7654 are located in two separate Station Address ( SA ), the first one at 0x00h and the second one at 0x34h. Be careful to select the proper SA when accessing register because some registers have the same address but are located in a different Station Address. Note that both sections of this device cannot bear the same I2C address.
Vertical Timing
The CS7654 encoder section can be configured to operate in any of four different analog timing modes: PAL, which is 625 vertical lines, 25 frames per second interlaced; NTSC, which is 525 vertical lines, 30 frames per second interlaced; and either PAL or NTSC in Progressive Scan, in which the display is non-interlaced. These modes are selected in the CONTROL_0 Register (0x00) at SA 0x00h.Note that there are several digital mode (scaler settings ) which will not have an equivalent analog timing mode. The CS7654 conforms to standard digital decompression dimensions and does not process digital input data for the active analog video half lines as they are typically in the over/underscan region of televisions. 240 active lines total per field are processed for NTSC, and 288 active lines total per field are processed for PAL. Frame vertical dimensions are 480 lines for NTSC and 576 lines for PAL. Table 3 specifies active line numbers for both NTSC and PAL.
Testability
The digital circuits are completely scanned by an internal scan chain, thus providing close to 100% fault coverage.
OPERATIONAL DESCRIPTION Reset Hierarchy
The CS7654 is equipped with an active low asynchronous reset input pin, RESET. RESET is used to initialize the internal registers and the internal state machines for subsequent default operation. See the electrical and timing specification section of this data sheet for specific CS7654 device RESET and power-on signal timing requirements and restrictions.
16
CS7654
Mode NTSC PAL NTSC Progressive-Scan PAL Progressive-Scan Field 1, 3; 2, 4 1, 3, 5, 7; 2, 4, 6, 8 NA NA Table 3. Vertical Timing
NTSC Vertical Timing (odd field)
Active Lines 22-261; 285-524 23-310; 336-623 22-261 23-310
Line HSYNC VSYNC
FIELD
3
4
5
6
7
8
9
10
NTSC Vertical Timing (even field)
Line HSYNC
VSYNC
264
265
266
267
268
269
270
271
FIELD
PAL Vertical Timing (odd field) Line
265
1
2
3
4
5
6
7
HSYNC VSYNC FIELD
PAL Vertical Timing (even field)
Line HSYNC VSYNC FIELD
311
312
313
314
315
316
317
318
Figure 4. Vertical Timing
NTSC Interlaced
The CS7654 supports analog NTSC-M, NTSC-J and PAL-M modes where there are 525 total lines per frame and two fixed 262.5-line fields per frame and 30 total frames occurring per second. NTSC in-
terlaced vertical timing is illustrated in Figure 5. Each field consists of one line for closed caption, 240 active lines of video, plus 21.5 lines of blanking.
17
CS7654
Analog Field 1
VSYNC Drops
523
524
525
1
2
3
4
5
6
7
8
9
10
22
Analog Field 2
261
262
263
264
265
266
267
268
269
270
271
272
284
285
Analog Field 3
VSYNC Drops
523
524
525
1
2
3
4
5
6
7
8
9
10
22
Analog Field 4
261
262
263
264
265
266
267
268
269
270
271
272
284
285
Burst begins with positive half-cycle
Burst begins with negative half-cycle
Figure 5. NTSC Video Interlaced Timing
PAL Interlaced
The CS7654 supports analog PAL modes B, D, G, H, I, N, and Combination N, in which there are 625 total lines per frame, two fixed 312.5 line fields per frame, and 25 total frames per second. Figure 7 illustrates PAL interlaced vertical timing. Each field consists of 287 active lines of video plus 25.5 lines.
NTSC). The common method is flawed: over time, the output display rate will overrun a system-clocklocked MPEG-2 decompressor and display a field twice every 8.75 seconds. NTSC non-interlaced timing is illustrated in Figure 7. PAL non-interlaced timing is illustrated in Figure 8.
Digital Video Input Modes
The CS7654 provides two different digital video input modes that are selectable through the IN_MODE bit in the CONTROL_0 Register at SA 0x00. In Mode 0 and upon RESET, the CS7654 defaults to output a solid color (one of a possible of 256 colors). The background color is selected by writing the BKG_COLOR Register (0x08) at SA 0x00. The colorspace of the register is RGB 3:3:2 and is unaffected by gamma correction. The default color following RESET is blue.
Progressive Scan
The CS7654 supports an analog progessive scan mode in which the video output is non-interlaced. This is accomplished by displaying only the odd video field for NTSC or PAL. To preserve precise MPEG-2 frame rates of 30 and 25 per second, the CS7654 displays the same odd field repetitively but alternately varies the field times. This mode is in contrast to other digital video encoders, which commonly support progressive scan by repetitively displaying a 262 line field (524/525 lines for
18
CS7654
VSYNC Drops Analog Field 1
620
621
622
623
624
625
1 Analog Field 2
2
3
4
5
6
7
23
24
308
309
310
311
312
313
314 Analog Field 3
315
316
317
318
319
320
336
337
620
621
622
623
624
625
1 Analog Field 4
2
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog Field 5
620
621
622
623
624
625
1 Analog Field 6
2
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog Field 7
620
621
622
623
624
625
1 Analog Field 8
2
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Burst Phase = 135 degrees relative to U
Burst Phase = 225 degrees relative to U
Figure 6. PAL Interlaced Timing
19
CS7654
Start of VSYNC Field 1
262
263
1
2
3
4
5 Field 2
6
7
8
9
10
22
261
262
1
2
3
4
5 Field 3
6
7
8
9
10
22
Start of VSYNC
262
263
1
2
3
4
5 Field 4
6
7
8
9
10
22
261
262
1
2
3
4
5
6
7
8
9
10
22
Burst begins with positive half-cycle Burst phase = reference phase = 180 0 relative to B-Y
Burst begins with negative half-cycle Burst phase = reference phase = 180 0 relative to B-Y
Figure 7. NTSC Video Non-Interlaced Progressive Scan Timing
In mode 1 the CS7654 displays the image captured by the camera.
Multi-standard Output Format Modes
The CS7654 supports a wide range of analog output formats compatible with worldwide broadcast standards. These formats include NTSC-M, NTSCJ, PAL-B/D/G/H/I, PAL-M, PAL-N, and PAL Combination N (PAL-Nc) which is the broadcast standard used in Argentina. After RESET, the CS7654 defaults to NTSC-M operation with ITU R.BT 601 analog timing. NTSC-J can also be supported in the Japanese format by turning off the 7.5 IRE pedestal through the PED bit in the CONTROL_1 Register (0x01) at SA 0x00. Output formats are configured by writing control registers with the values shown in Table 5.
(SC_SYNTH0/1/2/3). The NTSC subcarrier synthesizer is reset every four fields (every eight fields for PAL). The SC_SYNTH0/1/2/3 registers used together provide a 32-bit value that defaults to NTSC (43E0F83Eh) following RESET. Table 4 shows the 32-bit value required for each of the different broadcast formats.
Color Bar Generator
The CS7654 is equipped with a color bar generator that is enabled through the CBAR bit of the CONTROL_1 Register lodated at SA 0x00. The color bar generator works in master Mode only and has no effect on the video input/output timing. The color bar generator will override the video input pixel data. The output of the color bar generator is instantiated after the chroma interpolation filter and before the luma delay line. The generated color bar numbers are for 100% amplitude, 100% saturation NTSC EIA color bars or 100% amplitude, 100% satura-
Subcarrier Generation
The CS7654 automatically synthesizes NTSC and PAL color subcarrier clocks using the CLK frequency and four control registers
20
CS7654
VSYNC Drops Analog Field 1
309
310
311
312
313
1 Analog Field 2
2
3
4
5
6
7
23
24
308
309
310
311
312
1
2
3
4
5
6
7
23
24
Analog Field 3
309
310
311
312
313
1 Analog Field 4
2
3
4
5
6
7
23
24
308
309
310
311
312
1
2
3
4
5
6
7
23
24
Burst Phase = 135 degrees relative to U
Burst Phase = 225 degrees relative to U
Figure 8. PAL Video Non-Interlaced Progressive Scan Timing
System NTSC-M, NTSC-J PAL-B, D, G, H, I, N PAL-N (Argentina) PAL-M
Fsubcarrier 3.5795455 MHz 4.43361875 MHz 3.582056 MHz 3.579611 MHz Table 4.
Value (hex) 43E0F83E 54131596 43ED288D 43CDDFC7
tion PAL EBU color bars. For PAL color bars, the CS7654 generates NTSC color bar values, which are very close to standard PAL values.
out of this range to conform to the ITU-R BT.601 specifications. However for some applications it is useful to allow a wider input range. By setting the CLIP_OFF bit (CONTROL_6 register at Station Address 0x00) the allowed input range is extended between 0x01 - 0xFE ( 1 - 254 ) for both luma and chrominance values.
Super White/Super Black support
The ITU-R BT.601 recommendation limits the allowed range for the digital video data between 0x10 - 0xEB (16 - 235 ) for luma and between 0x10 - 0xF0 (16 - 240 ) for the chrominance values. This chip will clip any digital input value which is
21
CS7654
Address for SA 0x00 0x00 0x01 0x04 0x05 0x10 0x11 0x12 0x13 0x14
Register CONTROL_0 CONTROL_1 CONTROL_4 CONTROL_5 SC_AMP SC_SYNTH0 SC_SYNTH1 SC_SYNTH2 SC_SYNTH3
NTSC-M NTSC-J ITU ITU NTSC-M PALR.BT601 R.BT601 RS170A B,D,G,H,I 01h 12h 07h 78h 1Ch 3Eh F8h E0h 43h 01h 10h 07h 78h 1Ch 3Eh F8h E0h 43h 21h 16h 07h 78h 1Ch 3Eh F8h E0h 43h 41h 30h 07h 78h 15h 96h 15h 13h 54h
PAL-M 61h 12h 07h 78h 15h C7h DFh CDh 43h
PAL-N A1h 30h 07h 78h 15h 96h 15h 13h 54h
PAL-N Comb. (Argent) 81h 30h 07h 78h 15h 8Ch 28h EDh 43h
Table 5. Multi-standard Format Register Configurations
Note that 0x00 and 0xFF values are never allowed, since they are reserved for synchronization information.
22
CS7654
FILTER RESPONSES
1.3 Mhz. filter frequency response 0 1.3 Mhz. filter passband response
-10
0
-20 magnitude - dB magnitude - dB 0 1 2 3 4 frequency (Hz) 5 6 -0.1
-30
-0.2
-40
-0.3 -50 -0.4
-60
-70
-0.5 6 x 10
0
2
4 6 frequency (Hz)
8
10
12 x 10 5
Figure 9. 1.3 Mhz Chrominance low-pass filter transfer characteristic
650 Khz. filter frequency response 0
Figure 10. 1.3 Mhz Chrominance low-pass filter transfer characterstic (passband)
650 Khz. filter passband response 0
-5
-0.5
magnitude - dB
magnitude - dB 0 1 2 3 4 5 6 x 10
-10
-1
-15
-1.5
-20
-2
-25
-2.5
-30
-3 6 0 2 4 6 8 10 12 x 10 5
Figure 11. 650 kHz Chrominance low-pass filter transfer characteristic
Figure 12. 650 kHz Chrominance low-pass filter transfer characteristic (passband)
23
CS7654
Chroma Output Interpolator Pass band 1 0.8 -5 0.6 Magnitude Response (dB) Magnitude Response (dB) -10 -15 -20 -25 -30 -0.6 -0.8 -1 0 0.5 1 1.5 2 2.5 3 Frequency (MHz) 3.5 4 4.5 5 -35 -40 0 2 4 6 8 Frequency (MHz) 10 12 14 0.4 0.2 0 -0.2 -0.4 0 Luma Output Interpolation Filter Response at 27MHz full scale
Figure 13. Chrominance output interpolation filter transfer characteristic (passband)
Figure 14. Luminance interpolation filter transfer characteristic
Luma Output Interpolation Filter Response at 27 MHz (-3 dB) 0.5 0 Magnitude Response (dB) -0.5 -1 -1.5 -2 -2.5 -3 -3.5
0
1
2
3 4 5 Frequency (MHz)
6
7
8
Figure 15. Luminance interpolation filter transfer characterstic (passband)
24
CS7654
INTERNAL REGISTER STRUCTURE AND USER INTERFACE
The user interface describes the user's external view of the CS7654 and the basic control operations. These areas include digital data, analog output modes and organization, timing and synchronization signals, I2C interface, and miscellaneous controls. C ports: (1) a slave I C port called the primary I C port, and (2) a secondary I2C port with limited I2C master capabilities. The primary I2C port allows an external controller to control the CS7654 ( See Station Address section for more details on Station Address structure ). It is assumed the external controller will also directly control any other I2C slave devices on the camera board. This is the normal I2C operation mode of CS7654. The secondary I2C port, on the other hand, may be used to control all the other slave devices on a camera board through the CS7654 only. This feature is useful when the external I2C controller is used to control multiple cameras. When used in this configuration the P4BYTMODE pin (pin 46) of the CS7654 must be tied high and the device is operated in four-byte mode.
2
dress. The LSB of the station address is the R/W (data direction) bit. This bit is set LOW in the WRITE and ADDRESS SET packets, and it is set HIGH for READ packets. The master can read and write to non-existent registers within the selected device. WRITE operations will have no effect; READ operations will return a value of 00h.
Station Address
Each device on the I2C bus has a unique 7-bit address. An eighth bit, the R/W bit, determines if the current data transfer writes data to the slave device or reads data from the slave device. It is common to represent the station address and R/W bit as two 8bit station addresses, one address for write accesses and another address for read accesses. We will follow this practice. Please note that because the register of the CS7654 are physically implemented in two different banks, the use of two different Station Addresses are necessary. Therefore, to access the proper registers you must first select the proper Station Address. Both Station Adresses have to be different from one another or an internal register conflict will occur. The CS7654 default station address are 34h for writes and 35h for reads for the color processing section and 00h and 01h for the encoder portion of the CS7654. The station address can be changed by writing a new station address to register FFh. The value written to this register does not include the R/W bit. For example. The default station address (34h write / 35h read) will be stored as 1Ah in register FFh.
The CS7654 has two I2
2
Operating CS7654 in Normal I2C Configuration (Three-Byte Mode)
In normal mode, the CS7654 is connected as a slave device to an external I2C controller through the primary I2C port. The connection is done via a two-wire serial bus. Other I2C devices on the camera may also share the same serial bus. The external controller communicates with the I2C devices by sending and receiving short packets of 8-bit words in accordance with the I2C protocol. The packets contain the station address of the target device, the desired register address, and data. There are three packet formats: WRITE format, ADDRESS SET format, and READ format. Each packet is addressed to a device by the station ad-
Write Operations in Three-Byte Mode
The WRITE format consists of a three-byte packet. The first byte is the station address with the data direction bit set LOW to indicate a write. The second byte is the device register address (0..255). The third byte is the register data (0..255). No additional bytes are allowed.
25
CS7654
the previous WRITE operation or the previous ADDRESS SET operation.
CS7654 secondary I2C Byte Sequence READ Format Packet Details First Byte Station Address with LSB set HIGH; Source Device then Returns One Byte of Register Data (0..255) Second Byte Returned data from CS7654 External controller Table 8. READ Format Packet.
EPROM CS7615
primary I2C
To other sub-systems Figure 16. I2C configuration showing primary and secondary I2C busses.
Operating CS7654 in Four-Byte I2C Configuration
In this configuration the external controller talks only to the CS7654 through the primary I2C interface. All the other slave devices on the camera board are tied to the secondary I2C port of the CS7654. WRITE and READ packets only are defined in four-byte mode. Independent address set operations to slave devices on the secondary I2C bus is not allowed in four-byte mode. Four-byte mode is active when the P4BYTMODE pin (pin 46) is logic high.
Byte Sequence WRITE Format Packet Detail First Byte Station Address with LSB Set LOW Second Byte Device Register Address (0..255) Third Byte Register Data (0..255) Table 6. WRITE Format Packet
Address Set Operation
The ADDRESS SET format consists of a two-byte packet which sets the address of a subsequent READ operation. The first byte of the Station Address with the LSB (data direction bit) set LOW to indicate a write operation. The second byte is the register address (0..255). The ADDRESS SET format is the same as the WRITE format, without the register data (third byte).
Byte Sequence First Byte Second Byte ADDRESS SET format Packet Details Station Address with LSB Set LOW Device Register Address (0..255)
Write Operations in Four-Byte mode
All WRITE operations from an external controller, through the CS7654, to any slave device must use the four-byte mode; this includes writing to the CS7654 itself. The external controller sends a fourbyte WRITE command to the CS7654 which initiates a WRITE operation to the destination slave device and sets the I2CBUSY bit in the status register ( 01h at SA 0x34h ). The I2CBUSY bit is cleared when the write operation on the secondary bus is complete. The External controller can poll the status register to check if the CS7654 has completed the command. The CS7654 has a one-command-buffer which allows the external controller to queue one additional command while the current command is still being executed. If more than one command is sent before the I2CBUSY bit is cleared, the CS7654 saves only the last command and executes it after the current one is completed. Commands that involve writing
Table 7. ADDRESS SET Format Packet Operation
Read Operations in Three-Byte Mode
The READ operation may consist of two or more bytes. The first byte is the station address with the LSB (data direction bit) set HIGH indicating a read operation. The addressed device then sends one or more bytes back from the register last addressed by
26
CS7654
or reading only to CS7654 registers are not put in the queue but are executed immediately without affecting any transactions occurring on the master I2C interface. Any attempt by the external I2C controller to write to the CS7654 registers while the CS7654 is busy initializing from an external EEPROM will be ignored. However, reads from the CS7654 are allowed during this time. If, during a READ or WRITE operation to a slave device, the CS7654 fails to receive an acknowledge bit the execution of the command is aborted and the NODEV bit in the status register is set high. This bit remains set unless it is explicitly cleared by writing to it or a new command is written to CS7654.
Byte Sequence WRITE Format Packet Detail First Byte Station Address of CS7654 with LSB Set LOW Second Byte Station Address of target slave device with LSB Set LOW Third Byte Device Register Address (0..255) Fourth Byte Register Data (0..255) Table 9. Four-byte WRITE Format Packet
The READ-TRIGGER packet initiates a READ operation by the CS7654 from the target slave device on the secondary I2C bus. The status register in the CS7654 may be checked to see if the read operation has been completed. The I2CBUSY bit in status register 01h at SA 0x34h is set to zero when the operation is completed. On completion of a read cycle from the target device, the CS7654 places the data read into the Slave Data Hold register at address 19h at SA 0x34h. The external controller can read this data through the primary I2C port. This requires first performing an ADDRESS SET operation to set the address to 19h at SA 0x34h and then sending a one-byte station address indicating read to the CS7654. The data from register 19h at SA 0x34h is then returned by the CS7654.
Byte Sequence WRITE Format Packet Detail First Byte Station Address of CS7654 with LSB Set LOW Second Byte Station Address of CS7654 with LSB Set LOW Third Byte Slave Data Hold reg. address 19h Table 11. Address Set for Slave Data Hold register in Four-byte mode Byte Sequence READ Format Packet Details First Byte CS7654 Station Address with LSB set HIGH. Second Byte Returned data from register 19h of CS7654 Table 12. READ Format Packet.
Read Operations in Four-Byte Mode
The READ operation in four-byte mode first requires a three-byte READ-TRIGGER packet to the CS7654. The first byte is the station address of the CS7654 with the LSB set LOW. The second byte is the target slave device's station address with the LSB (data direction bit) set HIGH. The third byte is the register address (0..255).
Byte Sequence First Byte Second Byte Third Byte READ-TRIGGER format Packet Details CS7654 Station Address with LSB Set LOW Target device Station Address with LSB Set HIGH Device Register Address (0..255)
Initializing Slave Devices on Secondary I2C bus from an EPROM
An EPROM may be attached to the secondary I2C bus for initialization purposes. Resetting the CS7654 initiates a download of register values from the EPROM into any of the slave devices on the secondary I2C bus. The EPROM is assumed to be at station address A0h. If during initialization, the CS7654 does not receive an acknowledge bit from the EPROM, all transactions with the
27
Table 10. READ-TRIGGER packet in four-byte mode
CS7654
EPROM are aborted and the NODEV status bit is set in status register at address 01h at SA 0x34h. The data within the EPROM is formatted in threebyte packets that represent the destination address, register address, and data. After reading a packet, the CS7654 initiates an I2C bus cycle using the first byte as the device station address, the second byte as the device register address, and the third byte as the data being written to the device. If an acknowledge is received from the target device, the CS7654 will fetch the next 3 bytes from the EPROM and repeat the process. The only exception being the gamma table whose entire 256 bytes is transferred in one I2C write cycle. This process will continue until the total number of packets read equals the value in the EEPROM count register (registers 1Ah and 1Bh at SA 0x34h), a HALT command is executed, or NO ACKNOWLEDGE is received from the target device. While the CS7654 is downloading from the EPROM, the INITACT bit (register 01h bit3 at SA 0x34h) is set in the status register of CS7654. All attempts to write to CS7654 registers by an external controller will be ignored during this time. The SKIP command tells the CS7654 to skip to the address within the EEPROM specified by the Configuration Control registers (30h - 3Fh at SA 0x34h). The Configuration Control registers are used in pairs to provide a 11-bit EEPROM address. The Configuration Index Register determines which two of the 8 pairs will be used. The Configuration Index Register is loaded automatically after reset by the CS7654. The CS7654 will read from the GPIO port. If the read cycle is successful, the Configuration Index Register will contain the state of the lower 3 bits of the parallel I/O port. A set of shunts or DIP switches attached to the I/O port provides a convenient way to select up to 8 configurations. The SKIP command is executed by writing a 1 to bit 1 of the EEPROM Control Register (42h at SA 0x34h). The JUMP is similar to the SKIP command. The user loads a jump address into the Jump Control Registers (40h and 41h at SA 0x34h) and then executes the JUMP command by setting bit 2 of the EEPROM Control Register (42h at SA 0x34h) to a 1. The jump command may be used to reduce the amount of required EEPROM space by allowing multiple configurations to share common data. For example, three configurations may be necessary to adjust for three different CCD timings, but they may all share a common gamma table. The HALT command is used to stop the execution of the boot state machine. When all necessary data has been read from the EEPROM, writing a 1 to bit 0 (HALT) of the EEPROM Control Register will safely stop the boot process. The total number of packets that may be stored in the external EEPROM is 2k/3 or 682 3-byte commands. Gamma table packets contain 259bytes. A typical map of the EPROM table is shown in Figure 17. The only exception to this organization is data for the CS7654 gamma table. The data for the gamma table is organized as shown in Figure 18.
Controlling the Configuration Process
The simplest configuration would consist of an EPROM with one configuration file. In this case, the first commands in the EPROM should write the total number of packets in the EEPROM. This data is written to the EEPROM count high and low byte registers (registers 1Ah and 1Bh at SA 0x34h). Subsequent bytes would contain all the necessary data to configure the camera. This data will be read in a sequential fashion. If, however, multiple configurations are desired, the EEPROM may be programmed with multiple sets of data, and the CS7654 programmed to select one of 8 configurations. The appropriate configuration is defined by the 3 GPIO[2:0] pins. The CS7654 incorporates 3 commands to handle multiple configurations: SKIP, JUMP, and HALT.
28
CS7654
EPROM Block 000 (binary) Address 00h CS7654 station address[7] +W 1Ah (addrs of low byte Count) count value CS7654 station address[7] +W 1Bh (addrs of high byte Count) count value Dest. station address + W Dest. device address data value Dest. station address + W data [gamma loc FFh] CS7654 station address[7] +W 0Ch (gamma reg. addrs) data = select RGB ram data [gamma loc 00h] data [gamma loc 01h]
Figure 17. Map of EPROM table for initialization of registers
Figure 18. Map of EPROM table for storing gamma ram initialization data.
Reserved Registers and Test Pins
To ensure proper operation of the CS7654, connect and SCENABLE (pin 45) to ground, and connect TEST1 (pin 64) and TEST2 (pin 42) to VDD. Registers 23h - 26h at SA 0x34h must be set to a value of FFh after reset. All other reserved registers may be left in their default states.
General Purpose I/O Port
The CS7654 has a GPIO port and register that is available when the device is configured for I2C host interface operation. The GPIO [2:0] pins operate as input or outputs pins for the GPIO_DATA_REG Register (0x0A at SA 0x00h). The GPIO [2:0] pins are configured for input operation when the corre-
sponding GPIO_CTRL_REG [2:0] bits are set to 0 and output when set to 1. In GPIO input mode, the CS7654 will latch the data on the [2:0] pins into the corresponding bit locations of GPIO_DATA_REG when it detects register address 0x0A at SA 0x00h through the I2C interface. A detection of address 0x0A can happen in two ways. The first and most common way this will happen is when address 0x0A is written to the CS7654 via its I2C interface. The second method for detecting address 0x0A is implemented by accessing register address 0x09 at SA 0x00h through I2C. In I2C host interface operation, the CS7654 register address pointer will autoincrement to address 0x0A after an address 0x09 access ( at SA 0x00h ).
29
CS7654
ANALOG Analog Timing
All CS7654 analog timing and sequencing is derived from 27 MHz clock input. The analog outputs are controlled internally by the video timing generator in conjunction with master and slave timing. The video output signals perform accordingly for NTSC and PAL specifications. Being that the CS7654 is almost entirely a digital circuit, great care has been taken to guarantee analog timing and slew rate performance as specified in the NTSC and PAL analog specifications. Reference the Analog Parameters section of this data sheet for exact performance parameters. control register bits that are used to control internal digital amplifiers. The DAC output levels are defined by the following operations:
VREF/RISET = IREF (e.g., 1.232 V/4K = 308 A)
COMP_VID/Y/C outputs in low impedance mode:
VOUT (max) = IREF*112.88*37.5 = 1.304V
COMP_VID/Y/C outputs in high impedance mode:
VOUT (max) = IREF*28.22*150 = 1.304 V
DACs
The CS7654 is equipped with three independent, video-grade, current-output, digital-to-analog converters (DACs). They are 10-bit DACs operating at a 27 MHz two-times-oversampling rate. All three DACs are disabled and default to a low power mode upon RESET. Each DAC can be individually powered down and disabled. The output-currentper-bit of all three DACs is determined by the size of the resistor connected between the ISET_DAC pin and electrical ground.
VREF
The CS7654 can operate with or without the aid of an external voltage reference. The CS7654 is designed with an internal voltage reference generator that provides a vrefout signal at the VREF pin. The internal voltage reference is utilized by not making a connection to the VREF pin. The VREF pin can also be connected to an external precision 1.232 volt reference, which then overrides the internal reference.
Luminance DAC
The SVID_Y pin is driven from a 10-bit 27 MHz current output DAC that internally receives the SVID_Y, or luminance portion, of the video signal (black and white only). SVID_Y is designed to drive proper video levels into a 37.5 load. Reference the detailed electrical section of this data sheet for the exact SVID_Y digital to analog AC and DC performance data. A EN_L enable control bit in the Control Register 5 (0x05 at SA 0x00h) is provided to enable or disable the luminance DAC. For a complete disable and lower power operation the luminance DAC can be totally shut down via the SVIDLUM_PD control bit in the Control Register 4 (0x04 at SA 0x00h). In this mode, turn-on through the control register will not be instantaneous.
ISET-DAC
All three of the CS7654 digital to analog converter DACs are output current normalized with a common ISET-DAC device pin. The DAC output current per bit is determined by the size of the resistor connected between ISET-DAC pin and electrical ground. Typically a 4 K, 1% metal film resistor should be used. The ISET resistance can be changed by the user to accommodate varying video output attenuation via post filters and also to suit individual preferred performance. In conjunction with the ISET-DAC value, the user can also independently vary the chroma, luma and colorburst amplitude levels via host addressable
30
CS7654
Chrominance DAC
The SVID_C pin is driven from a 10-bit 27 MHz current output DAC that internally receives the SVID_C or chrominance portion of the video signal (color only). SVID_C is designed to drive proper video levels into a 37.5 load. Reference the detailed electrical section of this data sheet for the exact SVID_C digital to analog AC and DC performance data. A EN_C enable control register bit in the Control Register 1 (0x05 at SA 0x00h) is provided to enable or disable the chrominance DAC. For a complete disable and lower power operation the chrominance DAC can be totally shut down via the SVIDCHR_PD register bit in the Control Register 4 (0x04 at SA 0x00h). In this mode turn-on through the control register will not be instantaneous. disable and lower power operation, the COMP_VID DAC can be totally shut down via the COMDAC_PD control register bit in Control Register 4 (0x04 at SA 0x00h). In this mode turnon through the control register will not be instantaneous. Depending on the external resistor connected to the ISET_DAC pin the output drive of the DACs can be changed. There are two modes in which the DACs should either be operated in. An external resistor of 4 k must be connected to the ISET_DAC pin. The first mode is the high impedance mode (LOW_IMP bit set to 0). The DAC outputs will then drive a double terminated load of 300 and will output a video signal which conforms to the analog video specifications for NTSC and PAL. External buffers will be needed if the DAC output load differs from 300 . The second mode is the low impedence mode (LOW_IMP but set to 1). The DAC output will then drive a double terminated load of 75 and will output a video signal which conforms to the analog video specifications for NTSC and PAL. No external buffers are necessary, the ouputs can directly drive a television input. Note If some of the 3 DACs are not used, it is strongly recommended to power them down (see CONTROL_4 register) in order to reduce the power dissipation.
COMP_VID DAC
The COMP_VID pin is driven from a 10-bit 27 MHz current output DAC that internally receives a combined luma and chroma signal to provide composite video output. COMP_VID is designed to drive proper composite video levels into a 37.5 load. Reference the detailed electrical section of this data sheet for the exact COMP_VID digital to analog ac and dc performance data. The EN_COM enable control register bit, in Control Register 1 (0x05 at SA 0x00h), is provided to enable or disable the output pin. When disabled, there is no current flow from the output. For a complete
31
CS7654
REGISTER DESCRIPTION
Control Registers of encoder section :SA0x00
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B - 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D - 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 - 0x31 0x32 0x33 0x34 0x35 - 0x59 0x5A 0x61 - 0x7F Register Name control_0 control_1 control_2 control_3 control_4 control_5 control_6 RESERVED bkg_color gpio_ctrl_reg gpio_data_reg RESERVED SYNC_0 SYNC_1 I2C_ADR SC_AMP SC_SYNTH0 SC_SYNTH1 SC_SYNTH2 SC_SYNTH3 HUE_LSB HUE_MSB SCH PHASE ADJUST CC_EN CC_21_1 CC_21_2 CC_284_1 CC_284_2 RESERVED CB_AMP CR_AMP Y_AMP R_AMP G_AMP B_AMP BRIGHT_OFFSET RESERVED INT_EN INT_CLR STATUS_0 RESERVED STATUS_1 RESERVED Table 13. Encoder Control Registers 32 Type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only Defaultvalue 01h 02h 00h 00h 3Fh 00h 00h 03h 00h 00h 90h F4h 00h 1Ch 3Eh F8h E0h 43h 00h 00h 00h 00h 00h 00h 00h 00h 80h 80h 80h 80h 80h 80h 00h 00h 00h
04h
CS7654
Control Register 0 at SA 0x00h
Address Bit Number Bit Name Default Bit 0x00
7 0
CONTROL_0
6 TV_FMT 0 0 5
Read/Write
4 MSTR 0
Default Value = 01h
3 CCIR656 1 2 PROG 0 1 IN_MODE 0 0 CBCR_UV 1
Mnemonic selects the TV display format 000: 001: 010: 011: 100: 101: 110-111:
Function NTSC-M CCIR601 timing (default) NTSC-M RS170A timing PAL-B, D, G, H, I PAL-M PAL-N (Argentina) PAL-N (non Argentina) reserved
7:5
TV_FMT
4 3 2 1 0
Reserved CCIR656 PROG IN_MODE CBCR_UV
Set to 0 Set to 1 Progressive scanning enable (enable = 1) Input select (0 = solid background, 1 = use V [7:0] data) enable YCbCr to YUV conversion (1 = enable, 0 = disable)
Control Register 1 at SA 0x00h
Address Bit Number Bit Name Default Bit 0x01
7 LUM DEL 0 0
CONTROL_1
6 5
Read/Write
4 LPF_ON 0
Default Value = 02h
3 res Reserved 2 res Reserved 1 PED 1 0 res Reserved
CH BW 0
Mnemonic luma delay on the composite output 00:
Function no delay (default) 1 pixel clock delay 2 pixel clock delay 3 pixel clock delay
7:6
LUM DEL
01: 10: 11:
5 4 3 2 1 0
CH BW LPF ON Reserved Reserved PED Reserved
chroma lpf bandwidth (0 = 650 kHz, 1 = 1.3 Mhz) chroma lpf on/off (0 = off, 1 = on) Reserved Reserved Pedestal offset (0: 0 IRE, 1: 7.5 IRE) Reserved
33
CS7654
Control Register 2 at SA 0x00h
Address Bit Number Bit Name Default Bit
7:1 0
0x02
7 res
CONTROL_2
6 res 5
Read/Write
4 res Reserved res
Default Value = 00h
3 res 2 res 1 res 0 BU_DIS 0
Mnemonic
Reserved BU DIS
Function
Set to 0
Chroma burst disable (1 = disable)
Control Register 3 at SA 0x00h
Address Bit Number Bit Name Default Bit
7:1 0
0x03
7 res
CONTROL_3
6 res 5
Read/Write
4 res Reserved res
Default Value = 00h
3 res 2 res 1 res 0 CBAR 0
Mnemonic
Reserved CBAR
Function Set to 0 internal color bar generator (0 = off, 1 = on)
Control Register 4 at SA 0x00h
Address Bit Number Bit Name Default Bit
7:6 5
0x04
7 res
CONTROL_4
6 res
Read/Write
5 1 4 1
Default Value = 3Fh
3 1 2 res 1 res Reserved 0 res
COMDAC_PD SVIDLUM_PD SVIDCHR_PD
Reserved
Mnemonic
COMDAC_PD
Function Reserved power down composite DAC 0: power up, 1: power down power down luma s-video DAC 0: power up, 1: power down power down chroma s-video DAC 0: power up, 1: power down Reserved set to "111"
4
SVIDLUM_PD
3 2:0
SVIDCHR_PD -
Control Register 5 at SA 0x00h
Address Bit Number Bit Name 0x05
7 RSVD
CONTROL_5
6 LOW IMP 5
Read/Write
4 EN L
Default Value = 00h
3 EN C 2 res 1 res 0 res
EN COM
34
CS7654
Default Bit
7 6 5 4 3 2:0 0 0 0 0 0 Reserved
Mnemonic
LOW IMP EN COM EN L EN C -
Function reserved selects between high output impedance (0) or low output impedance (1) mode of DACs enable DAC for composite output 0: tri-state, 1: enable enable s-video DAC for luma output 0: tri-state, 1: enable enable s-video DAC for chroma output 0: tri-state, 1: enable Reserved set to 0
Control Register 6 at SA 0x00h
Address Bit Number Bit Name Default Bit
7 6 5:0
0x06
7 res 0
CONTROL_6
6 CLIP OFF 0 5 res 0
Read/Write
4 res 0
Default Value = 00h
3 res 0 2 res 0 1 res 0 0 res 0
Mnemonic
res CLIP OFF res
Function
set to 0
Clipping input signals disable (0: clipping active 1: no clipping)
set to 0
Background Color Register at SA 0x00h
Address Bit Number Bit Name Default Bit
7:0
0x08
7 0
BKG_COLOR Read/Write
6 0 5 0 4
Default Value = 03h
3 BG 0 2 0 1 1 0 1
0
Mnemonic
BG
Function Background color (7:5 = R, 4:2 = G, 1:0 = B) (default is 0000 0011 - blue)
GPIO Control Register at SA 0x00h
Address Bit Number Bit Name Default Bit
2:0
0x09
7 res
GPIO__REG
6 res 5 res
Read/Write
4 res
Default Value = 00h
3 res 2 0 1 0 0 0
GPR_CNTRL
Mnemonic
GPR CNTRL
Function Input(0)/output(1) control of GPIO registers (bit 0: GPIO(0), bit 2: GPIO(2))
35
CS7654
GPIO Data Register at SA 0x00h
Address Bit Number Bit Name Default Bit
2:0
0x0A
7 res
GPIO_REG
6 res 5
Read/Write
4
Default Value = 00h
3 GPIO REG res 2 0 1 0 0 0
res
res
Mnemonic
GPIO REG
Function GPIO data register ( data is output on GPIO bus if appropriate bit in address 09 is set to "1", otherwise data is input/output through I2C)- This register is only accessible in I2C mode.
Sync Register 0 at SA 0x00h
Address Bit Number Bit Name Default Bit
7:0
0x0D
7 res 1
Sync_0
6 res 0 5
Read/Write
4 res 1 res 0
Default Value = 90h
3 res 0 2 res 0 1 res 0 0 res 0
Mnemonic
Reserved
Function
Sync Register 1 at SA 0x00h
Address Bit Number Bit Name Default Bit
7:0
0x0E
7 res 1
Sync_1
6 res 1 5 res 1
Read/Write
4 res 1
Default Value = F4h
3 res 0 2 res 1 1 res 0 0 res 0
Mnemonic
res
Function
res
I2C Address Register of TV encoder at SA 0x00h
Address Bit Number Bit Name Default Bit
7 6:0
0x0F
7 RESERVED 0
I2C_ADR
6 0 5 0
Read/Write
4 0
Default Value = 00h
3 I2C ADR 0 0 0 0 2 1 0
Mnemonic
I2C
Function reserved I2C device address (programmable) do not program to 34h
36
CS7654
Subcarrier Amplitude Register at SA 0x00h
Address Bit Number Bit Name Default Bit
7:0
0x10
7 0
SC_AMP
6 0 5 0
Read/Write
4
Default Value = 1Ch
3 BU AMP 1 2 1 1 0 0 0
1
Mnemonic
BU AMP
Function Color burst amplitude
Subcarrier Synthesis Register at SA 0x00h
Address 0x11 0x12 0x13 0x14 Bits
7:0 7:0 7:0 7:0
SC_SYNTH0 SC_SYNTH1 SC_SYNTH2 SC_SYNTH3 Mnemonic
CC 0 CC 1 CC 2 CC 3
Read/Write
Default Value = 3Eh F8h E0h 43h Function
Register
SC_SYNTH0 SC_SYNTH1 SC_SYNTH2 SC_SYNTH3
Subcarrier synthesis bits 7:0 Subcarrier synthesis bits 15:8 Subcarrier synthesis bits 23:16 Subcarrier synthesis bits 31:24
Hue LSB Adjust Register at SA 0x00h
Address Bit Number Bit Name Default Bit
7:0
0x15
7 0
HUE_LSB
6 0 5 0
Read/Write
4
Default Value = 00h
3 HUE LSB 0 2 0 1 0 0 0
0
Mnemonic
HUE LSB
Function 8 LSBs for hue phase shift
Hue MSB Adjust Register at SA 0x00h
Address Bit Number Bit Name Default Bit
7:2 1:0
0x16
7 0
HUE_MSB
6 0 5 0
Read/Write
4 0 RESERVED
Default Value = 00h
3 0 2 0 1 MSB 0 0 0
Mnemonic
HUE MSB
Function reserved 2 MSBs for hue phase shift
37
CS7654
SCH Sync Phase Adjust at SA 0x00h
Address Bit
7:0
0x17 Mnemonic
SCH
SCH
Read/Write
Default Value = 00h Function
Default - 00h in increments of 1.4 degree per bit up to 360
Closed Caption Enable Register at SA 0x00h
Address Bit Number Bit Name Default Bit
7:2 1 0
0x18
7 0
CC_EN
6 0 5 0
Read/Write
4 0 RESERVED
Default Value = 00h
3 0 2 0 1 EN_284 0 0 EN_21 0
Mnemonic
CC EN[1] CC EN[0]
Function reserved enable closed caption for line 284 enable closed caption for line 21
Closed Caption Data Register at SA 0x00h
Address 0x19 0x1A 0x1B 0x1C Mnemonic
CC_21_1 CC_21_2 CC_284_1 CC_284_2
CC_21_1 CC_21_2 CC_284_1 CC_284_2
Read/Write
Default Value = 00h 00h 00h 00h Function
Bit
7:0 7:0 7:0 7:0
first closed caption databyte of line 21 second closed caption databyte of line 21 first closed caption databyte of line 284 second closed caption databyte of line 284
Filter Register 0 at SA 0x00h
Address Bit Number Bit Name Default Bit
7:0
0x22
7 1
CB_AMP
6 0 5 0
Read/Write
4
Default Value = 80h
3 U_AMP 0 2 0 1 0 0 0
0
Mnemonic
U_AMP
Function U(Cb) amplitude coefficient
Filter Register 1 at SA 0x00h
Address Bit Number 0x23
7
CR_AMP
6 5
Read/Write
4
Default Value = 80h
3 2 1 0
38
CS7654
Bit Name Default Bit
7:0 V_AMP 1 0 0 0 0 0 0 0
Mnemonic
V_AMP
Function V(Cr) amplitude coefficient
Filter Register 2 at SA 0x00h
Address Bit Number Bit Name Default Bit
7:0
0x24
7 1
Y_AMP
6 0 5 0
Read/Write
4
Default Value = 80h
3 Y_AMP 0 2 0 1 0 0 0
0
Mnemonic
Y_AMP
Function Luma amplitude coefficient
Filter Register 6 at SA 0x00h
Address Bit Number Bit Name Default Bit
7:0
0x28
7 0
Bright_Offsett
6 0 5 0
Read/Write
4 0
Default Value = 00h
3 0 2 0 1 0 0 0
BRIGHTNESS_OFFSET
Mnemonic
BRGHT_OFFSET
Function Brightness adjustment ( range: -128 to +127)
39
CS7654
Control Register of Color Space Processor Section: SA 0x34h
Address [00] [01] [02] [03] [04] [05] [06] [07] [08] [09] [0A] [0B] [0C] [0D] [0E] [0F] [10] [11] [12] [13] [14] [15] [16] [17] [18]
[19] [1A] [1B] [1C] [1D] [1E] [1F] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [2A] [2B]
Register Name Master reset Status Pin i/o control Digital gain Scaler control Feature control Operation control 1 Operation control 2 Red balance Blue balance Red saturation Blue saturation Gamma correction Reserved Reserved Reserved YR coefficient CrR coefficient CbR coefficient YG coefficient CrG coefficient CbG coefficient YB coefficient CrB coefficient CbB coefficient
Slave data hold EEPROM count LSB EEPROM count MSB Version_major Version_minor Reserved Reserved Low power Reserved Reserved Anti-alias Reserved Reserved Reserved Flare control 1 Flare control 2 Flare control 3 Flare control 4 Flare control 5
Type r/w r only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
Defaultvalue 00h 00h 00h 08h 00h 00h 0Dh 00h 80h 80h 80h 80h 01h
r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r only r only
80h 7Ch E0h 80h E4h DCh 80h ECh 7Ch 00h 00h 00h FDh 00h
r/w
00h
r/w
00h
r/w r/w r/w r/w r/w
00h 00h 00h 00h 00h
Table 14. DSP Control Register
40
CS7654
Address
[2C] [2D] [2E] [2F] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [3A] [3B] [3C] [3D] [3E] [3F] [40] [41] [42] [43] [44] [FE] [FF]
Register Name
Flare control 6 Scaler control 1 Scaler control 2 Scaler control 3 Config 0 Config 1 Config 2 Config 3 Config 4 Config 5 Config 6 Config 7 Config 8 Config 9 Config 10 Config 11 Config 12 Config 13 Config 14 Config 15 Jump 0 Jump 1 EEPROM control Config index Reserved Reserved Station address
Type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
Defaultvalue 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
r/w
1Ah
Table 14. DSP Control Register (Continued)
Master Reset Register (00h at SA 0x34h )
7 res 6 res 5 res 4 res Reserved 3 res 2 res 1 res 0 MR W
MR
Setting bit MR0 to logic high will initiate a CS7654 master reset equivalent to executing an external reset using the RESET pin. All registers will be placed in their default state, and the download of any external EPROM present on the secondary I2C bus will be initiated. The bit is self-cleared.
Status Register (01h at SA 0x34h)
7 res Reserved 6 P4BYTE R 5 res Reserved 4 HIZENB R 3 INITACT R 2 I2CBUSY R 1 NODEV R 0 EVNFLD R
EVNFLD NODEV
Logic high indicates even field of interline-transfer CCD. Logic low indicates odd field of interline-transfer CCD. This bit provides a course means of synchronizing to the field rate. Logic high indicates that the addressed slave device on the secondary I2C bus did not respond.
41
CS7654
I2CBUSY INITACT HIZENB P4BYTE Logic high indicates that the CS7654 secondary I2C master is busy accessing the addressed slave device. Logic high indicates the CS7654 master is busy initializing registers from the external I2C EEPROM on the secondary I2C bus (if present). Pin 44 status. Pin 46 status.
PIN I/O Control (02h at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 res Reserved 1 res Reserved 0 PLLOUT R/W
PLLOUT
Logic high enables the PLL clock output to the CS7615 (pin 51).
Digital Gain Register (03h at SA 0x34h)
7 res 6 res Reserved 5 res 4 DG4 3 DG3 2 DG2 R/W 1 DG1 0 DG0
DG[0:4]
Controls the digital gain applied to the SVID_Y (Luminance) signal after the RGB to YCrCb converter block. The range of gains are from 0 to 31/8 in increments of 1/8. A gain of 0, indicates no brightness.
Scaler Control (04h at SA 0x34h)
7 res Reserved 6 res 5 res Reserved 4 res Reserved 3 CUSTOM R/W 2 MODE2 1 MODE1 R/W 0 MODE0
MODE[2:0] CUSTOM
Selects 1 of 8 pre-defined scaling ratios. When set, scaler uses custom values held in registers 2Dh-2Fh.
Feature Control Register (05h at SA 0x34h)
7 res 6 res Reserved 5 res 4 CHROFF R/W 3 LUMOFF R/W 2 GAMON R/W 1 AWB R/W 0 res Reserved
AWB
The Automatic White Balance procedure is initiated by pointing to a white scene and setting this bit high. The bit will return a logic high while the AWB procedure is in progress. Setting this bit low will have no effect. This bit will always be read as a "0" when the AWB is not in progress. The gamma correction from the gamma ram look up table is applied to the video signal in R-GB space when this bit is set high. The gamma ram is a fully user programmable, 256 entry look up table. Setting LUMOFF bit high disables the luma peaking filter. Setting the CHROFF bit high disables the chroma low-pass filter for minimizing color aliasing.
GAMON
LUMOFF CHROFF
42
CS7654
Operational Control Register (06h at SA 0x34h)
7 res Reserved 6 res Reserved 5 res Reserved 4 INREF R/W 3 OE R/W 2 POSPIX R/W 1 EBLU R/W 0 OBLU R/W
OBLU EBLU POSPIX
Logic high causes the first line after VREF of the odd field to be processed as a BLUE line. Logic low causes the first line of the odd field to be processed as a RED line. Logic high causes the first line after VREF of the even field to be processed as a BLUE line. Logic low causes the first line of the even field to be processed as a RED line. Logic "1" causes the first pixel of the first line to be treated as a positive pixel in the color separation block. Logic "0" causes the first pixel to be treated as a negative pixel. Try toggling this bit if the colors appear "reversed." The Output Enable Bit operates in conjunction with the external HIZEN Pin, as illustrated in Table 15. OE Bit 0 0 1 1 HIZEN Pin 0 1 0 1 Digital Outputs High-Z High-Z High-Z Enabled
OE
Table 15. OE Pin and Bit Operation INREF Logic "1" causes CS7654 to accept HREF input and VREF input pins as the reference inputs signals. EAV and SAV codes in the CCD data stream are ignored. Logic "0" causes the internal de-formatter to decode and follow the embedded EAV and SAV codes sent from the CCD digitizer (as with the CS7615).
Operational Control Register II (07h at SA 0x34h)
7 TEST_AA R/W 6 CLIP_OFF R/W 5 res Reserved 4 res Reserved 3 res Reserved 2 res Reserved 1 res Reserved 0 res Reserved
CLIP_OFF TEST_AA
When set, excludes only 00 and FF from output data. Otherwise ITU BT 601 definition This bit is reserved for test purposes and may be set as a 1 or a 0.
Red Balance Register (08h at SA 0x34h)
7 RB7 6 RB6 5 RB5 4 RB4 R/W 3 RB3 2 RB2 1 RB1 0 RB0
RB[7:0]
The Red Balance register controls the red contribution to the R-Y chrominance signal. When the register value is 00h, the red contribution is minimized; when the register value is FFh, the red contribution is maximized. When the AWB correction is in progress, this register value is adjusted such that the absolute magnitude of the R-Y signal is minimized.
43
CS7654
Blue Balance Register (09h at SA 0x34h)
7 BB7 6 BB6 5 BB5 4 BB4 R/W 3 BB3 2 BB2 1 BB1 0 BB0
BB[7:0]
The Blue Balance register controls the blue contribution to the B-Y chrominance signal. When the register value is 00h, the blue contribution is minimized; when the register value is FFh, the blue contribution is maximized. When the AWB correction is in progress, this register value is adjusted such that the absolute magnitude of the B-Y signal is minimized.
Red Saturation Register (0Ah at SA 0x34h)
7 RS7 6 RS6 5 RS5 4 RS4 R/W 3 RS3 2 RS2 1 RS1 0 RS0
RS[7:0]
The Red Saturation register value controls the amplitude of the R-Y chrominance signal. When the register value is 00h, the amplitude of the R-Y is minimized; when the register value is FFh, the amplitude of the R-Y is maximized.
Blue Saturation Register (0Bh at SA 0x34h)
7 BS7 6 BS6 5 BS5 4 BS4 R/W 3 BS3 2 BS2 1 BS1 0 BS0
BS[7:0]
The Blue Saturation register value controls the amplitude of the B-Y chrominance signal. When the register value is 00h, the amplitude of the B-Y is minimized; when the register value is FFh, the amplitude of the B-Y is maximized.
Gamma Correction Register (0Ch at SA 0x34h)
Writing to the gamma register (0Ch at SA 0x34h) selects the R, G, and/or B RAM. Continuing data writes without sending a stop bit after the register write results in writes to the ram locations starting with 00h and continuing to FFh. Reads from register 0Ch function in a similar way. NOTE: All three gamma rams may be selected for simultaneous writes, but read should be done one ram table at a time.
7 GC7 6 GC6 5 GC5 4 GC4 R/W 3 GC3 2 GC2 1 GC1 0 GC0
GC0 GC1 GC2 GC[0:7]
Logic "1" selects BLUE gamma RAM for subsequent access. Logic "1" selects GREEN gamma RAM for subsequent ram access. Logic "1" selects RED gamma RAM for subsequent ram access. Provide R/W access to RAM after gamma RAM table has been selected.
Test Control A Register (0Eh at SA 0x34h)
This register is reserved
44
CS7654
Test Control B Register (0Fh at SA 0x34h)
This register is reserved.
YR Coefficient Register (10h at SA 0x34h)
7 YR7 6 YR6 5 YR5 4 YR4 R/W 3 YR3 2 YR2 1 YR1 0 YR0
Color separation and color space conversion coefficient.
CrR Coefficient Register (11h at SA 0x34h)
7 CrR7 6 CrR6 5 CrR5 4 CrR4 R/W 3 CrR3 2 CrR2 1 CrR1 0 CrR0
Color separation and color space conversion coefficient.
CbR Coefficient Register (12h at SA 0x34h)
7 CbR7 6 CbR6 5 CbR5 4 CbR4 R/W 3 CbR3 2 CbR2 1 CbR1 0 CbR0
Color separation and color space conversion coefficient.
YG Coefficient Register (13h at SA 0x34h)
7 YG7 6 YG6 5 YG5 4 YG4 R/W 3 YG3 2 YG2 1 YG1 0 YG0
Color separation and color space conversion coefficient.
CrG Coefficient Register (14h at SA 0x34h)
7 CrG7 6 CrG6 5 CrG5 4 CrG4 R/W 3 CrG3 2 CrG2 1 CrG1 0 CrG0
Color separation and color space conversion coefficient.
45
CS7654
CbG Coefficient Register (15h at SA 0x34h)
7 CbG7 6 CbG6 5 CbG5 4 CbG4 R/W 3 CbG3 2 CbG2 1 CbG1 0 CbG0
Color separation and color space conversion coefficient.
YB Coefficient Register (16h at SA 0x34h)
7 YB7 6 YB6 5 YB5 4 YB4 R/W 3 YB3 2 YB2 1 YB1 0 YB0
Color separation and color space conversion coefficient.
CrB Coefficient Register (17h at SA 0x34h)
7 CrB7 6 CrB6 5 CrB5 4 CrB4 R/W 3 CrB3 2 CrB2 1 CrB1 0 CrB0
Color separation and color space conversion coefficient.
CbB Coefficient Register (18h at SA 0x34h)
7 CbB7 6 CbB6 5 CbB5 4 CbB4 R/W 3 CbB3 2 CbB2 1 CbB1 0 CbB0
Color separation and color space conversion coefficient.
Slave Data Hold Register (19h at SA 0x34h)
When an external I2C controller initiates a register read from a slave device on the secondary I2C bus through CS7654, the returned data is placed in this register. The external controller may then read the data from the Slave Data Hold register. This register is read only.
EPROM Count Low Byte Register (1Ah at SA 0x34h)
Lower byte of the number of triple-bytes to be read from EPROM upon reset of CS7654. This register is read only.
EPROM Count High Byte Register (1Bh at SA 0x34h)
Upper byte of the number of triple-bytes to be read from EPROM upon reset of CS7654. This register is read only.
Version (Major) Register (1Ch at SA 0x34h)
The major version register (device ID) in the CS7654 is assigned the value FDh. This register is read only.
Version (Minor) Register (1Dh at SA 0x34h)
The minor version register in CS7654 rev A. is assigned the value 00h. With each minor revision the value is increased by 1. This register is read only. 46
CS7654
Low Power Register (20h at SA 0x34h)
7 res 6 res 5 res 4 res Reserved 3 res 2 res 1 res 0 PD R/W
PD
Setting bit PD to "1" will place the CS7654 in low power mode.
Test Enable Register (21h at SA 0x34h)
This register is reserved.
Reserved Register (22h at SA 0x34h)
This register is reserved and returns a valud of 00 when read.
Anti-Alias (23h at SA 0x34h)
This register is reserved and must be set to 08h for normal operation.
Test_AA2 (24h at SA 0x34h)
This register is reserved and must be set to FFh for normal operation
Test_AA3 (25h at SA 0x34h)
This register is reserved and must be set to FFh for normal operation
Test_AA4 (26h at SA 0x34h)
This register is reserved and must be set to FFh for normal operation
Flare Control 1 (27h at SA 0x34h)
7 Y_THR9 6 Y_THR8 5 Y_THR7 4 Y_THR6 R/W 3 Y_THR5 2 Y_THR4 1 Y_THR3 0 Y_THR2
Y_THR[9:2]
Flare control filter Y threshold bits 9-2 (MSB). (Bits 1 and 0 set to 0.)
Flare Control 2 (28h at SA 0x34h)
7 Cr_L9 Cr_L[9:2] 6 Cr_L8 5 Cr_L7 4 Cr_L6 R/W 3 Cr_L5 2 Cr_L4 1 Cr_L3 0 Cr_L2
Flare control filter Cr low threshold bits 9-2 (MSB).
47
CS7654
Flare Control 3 (29h at SA 0x34h)
7 Cb_L9 Cb_L[9:2] 6 Cb_L8 5 Cb_L7 4 Cb_L6 R/W 3 Cb_L5 2 Cb_L4 1 Cb_L3 0 Cb_L2
Flare control filter Cb low threshold bits 9-2 (MSB). (Bits 1 and 0 set to 0.)
Flare Control 4 (2Ah at SA 0x34h)
7 Cr_H9 Cr_H[9:2] 6 Cr_H 5 Cr_H7 4 Cr_H6 R/W 3 Cr_H5 2 Cr_H4 1 Cr_H3 0 Cr_H2
Flare control filter Cr high threshold bits 9-2 (MSB).
Flare Control 5 (2Bh at SA 0x34h)
7 Cb_H9 Cb_H[9:2] 6 Cb_H8 5 Cb_H7 4 Cb_H6 R/W 3 Cb_H5 2 Cb_H4 1 Cb_H3 0 Cb_H2
Flare control filter Cb high threshold bits 9-2 (MSB). (Bits 1 and 0 set to 0.)
Flare Control 6 (2Ch at SA 0x34h)
7 Cb_H1 R/W Cr_L[1:0] Cb_L[1:0] Cr_H[1:0] Cb_H[1:0] 6 Cb_H0 5 Cr_H1 R/W 4 Cr_H0 3 Cb_L1 R/W 2 Cb_L0 1 Cr_L1 R/W 0 Cr_L0
Flare control filter Cr low threshold bits 1 and 0. Flare control filter Cb low threshold bits 1 and 0. Flare control filter Cr high threshold bits 1 and 0. Flare control filter Cb high threshold bits 1 and 0.
Scaler Control 1 (2Dh at SA 0x34h)
7 BYPASS1 R/W PLL_M[4:0] BYPASS[1:0] 6 BYPASS0 5 res Reserved 4 PLL_M4 3 PLL_M3 2 PLL_M2 R/W 1 PLL_M1 0 PLL_M0
This is the PLL M value when the CUSTOM bit (bit 3 register 04h) is set. See PLL section.
Scaler Control 2 (2Eh at SA 0x34h)
7 HALF R/W PLL_N[4:0] HALF 6 res Reserved 5 res 4 PLL_N4 3 PLL_N3 2 PLL_N2 R/W 1 PLL_N1 0 PLL_N0
This is the PLL N value when the CUSTOM bit (bit 3 register 04h at Sets the internal PLL reference clock to 1/2 the input clock.
SA 0x34h) is set.
48
CS7654
Scaler Control 3 (2Fh at SA 0x34h)
7 OFFSET7 OFFSET[7:0] 6 OFFSET6 5 OFFSET5 4 OFFSET4 R/W 3 OFFSET3 2 OFFSET2 1 OFFSET1 0 OFFSET0
This value controls the offset fo the internal Scaler.
Configuration Control 0 (30h at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 SKP010 1 SKP09 R/W 0 SKP08
This register contains the 3 MSBs of the EEPROM address used when the SKIP bit is set (bit1 register 42h at
SA
0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 00h. Configuration Control 1 (31h at SA 0x34h)
7 SKP07 6 SKP06 5 SKP05 4 SKP04 R/W 3 SKP03 2 SKP02 1 SKP01 0 SKP00
This register contains the 8 LSBs of the EEPROM start address used when the SKIP bit is set (bit1 register 42h at SA 0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 00h.
Configuration Control 2 (32h at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 SKP110 1 SKP19 R/W 0 SKP18
This register contains the 3 MSBs of the EEPROM address used when the SKIP bit is set (bit1 register 42h at
SA
0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 01h. Configuration Control 3 (33h at SA 0x34h)
7 SKP17 6 SKP16 5 SKP15 4 SKP14 R/W 3 SKP13 2 SKP12 1 SKP11 0 SKP10
This register contains the 8 LSBs of the EEPROM start address used when the SKIP bit is set (bit1 register 42h at SA 0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 01h.
Configuration Control 4 (34h at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 SKP210 1 SKP29 R/W 0 SKP28
This register contains the 3 MSBs of the EEPROM address used when the SKIP bit is set (bit1 register 42h at
SA
0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 02h.
49
CS7654
Configuration Control 5 (35h at SA 0x34h)
7 SKP27 6 SKP26 5 SKP25 4 SKP24 R/W 3 SKP23 2 SKP22 1 SKP21 0 SKP20
This register contains the 8 LSBs of the EEPROM start address used when the SKIP bit is set (bit1 register 42h at
SA 0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 02h. Configuration Control 6 (36h at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 SKP310 1 SKP39 R/W 0 SKP38
This register contains the 3 MSBs of the EEPROM address used when the SKIP bit is set (bit1 register 42h at
SA
0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 03h. Configuration Control 7 (37h at SA 0x34h)
7 SKP37 6 SKP36 5 SKP35 4 SKP34 R/W 3 SKP33 2 SKP32 1 SKP31 0 SKP30
This register contains the 8 LSBs of the EEPROM start address used when the SKIP bit is set (bit1 register 42h at
SA 0x34h) and the Configuration Index Register (43h at SA 0x34h ) is set to 03h. Configuration Control 8 (38h at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 SKP410 1 SKP49 R/W 0 SKP48
This register contains the 3 MSBs of the EEPROM address used when the SKIP bit is set (bit1 register 42h at
SA
0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 04h. Configuration Control 9 (39h at SA 0x34h)
7 SKP47 6 SKP46 5 SKP45 4 SKP44 R/W 3 SKP43 2 SKP42 1 SKP41 0 SKP40
This register contains the 8 LSBs of the EEPROM start address used when the SKIP bit is set (bit 1 register 42h at SA 0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 04h.
Configuration Control 10 (3Ah at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 SKP510 1 SKP59 R/W 0 SKP58
This register contains the 3 MSBs of the EEPROM address used when the SKIP bit is set (bit 1 register 42h at
SA
0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 05h.
50
CS7654
Configuration Control 11 (3Bh at SA 0x34h)
7 SKP57 6 SKP56 5 SKP55 4 SKP54 R/W 3 SKP53 2 SKP52 1 SKP51 0 SKP50
This register contains the 8 LSBs of the EEPROM start address used when the SKIP bit is set (bit 1 register 42h at SA 0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 05h.
Configuration Control 12 (3Ch at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 SKP610 1 SKP69 R/W 0 SKP68
This register contains the 3 MSBs of the EEPROM address used when the SKIP bit is set (bit 1 register 42h at
SA
0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 06h. Configuration Control 13 (3Dh at SA 0x34h)
7 SKP67 6 SKP66 5 SKP65 4 SKP64 R/W 3 SKP63 2 SKP62 1 SKP61 0 SKP60
This register contains the 8 LSBs of the EEPROM start address used when the SKIP bit is set (bit 1 register 42h at SA 0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 06h.
Configuration Control 14 (3Eh at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 SKP710 1 SKP79 R/W 0 SKP78
This register contains the 3 MSBs of the EEPROM address used when the SKIP bit is set (bit 1 register 42h at
SA
0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 07h. Configuration Control 15 (3Fh at SA 0x34h)
7 SKP77 6 SKP76 5 SKP75 4 SKP74 R/W 3 SKP73 2 SKP72 1 SKP71 0 SKP70
This register contains the 8 LSBs of the EEPROM start address used when the SKIP bit is set (bit 1 register 42h at SA 0x34h) and the Configuration Index Register (43h at SA 0x34h) is set to 07h.
Jump Control 0 (40h at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 JMP10 1 JMP9 R/W 0 JPM8
This register contains the 3 MSBs of the EEPROM address used when the JUMP bit is set (bit 2 register 42h at SA
0x34h).
51
CS7654
Jump Control 1 (41h at SA 0x34h)
7 JMP7 6 JMP6 5 JMP5 4 JMP4 R/W 3 JMP3 2 JMP2 1 JMP1 0 JPM0
This register contains the 8 LSBs of the EEPROM start address used when the JUMP bit is set (bit 2 register 42h
at SA 0x34h).
EEPROM Control (42h at
7 res 6 res
SA 0x34h)
5 res 4 res 3 res 2 JUMP 1 SKIP R/W 0 HALT
State machine commands for loading EEPROM data after reset. (see extended EPROM configuration) HALT SKIP Writing a 1 to this bit stops the reading of EEPROM data. Writing a 1 to this bit forces the next EEPROM read cycle to occur at the address held in the Configuration Control (n) register, where "n" is the value held in the Configuration Index Register (43h at SA 0x34h) Writing a 1 to this bit forces the next EEPROM access to occur at the address held in registers 40h and 41h at SA 0x34h .
JUMP
Configuration Index Register (43h at SA 0x34h)
7 res 6 res 5 res Reserved 4 res 3 res 2 SW2 1 SW1 R/W 0 SW0
This contains the DIP switch status at reset. (see extended EPROM configuration) The value of this register selects the appropriate Configuration register when the SKIP command is executed.
Reserved Registers (44h - FEh at SA 0x34h)
These registers are reserved and return a value of 00h when read.
Station Address Register (FFh at SA 0x34h)
7 res Reserved 6 SA6 5 SA5 4 SA4 3 SA3 R/W 2 SA2 1 SA1 0 SA0
CS7654 station address of the color processor, 7 MSBs (the LSB of the complete 8-bit station address is determined by the LSB which acts as a read/write direction bit).
52
CS7654
BOARD DESIGN AND LAYOUT CONSIDERATIONS
The printed circuit layout should be optimized for lowest noise on the CS7654 placed as close to the output connectors as possible. All analog supply traces should be as short as possible to minimize inductive ringing. A well designed power distribution network is essential in eliminating digital switching noise. The ground planes must provide a low-impedance return path for the digital circuits. A PC board with a minimun of four layers is recommended. The ground layer should be used as a shield to isolate noise from the analog traces. The top layer (1) should be reserved for analog traces but digital traces can share this layer if the digital signals have low edge rates and switch little current or if they are separated from the analog traces by a signigicant distance (dependent on their frequency content and current). The second layer should then be the ground plane followed by the analog power plane on layer three and the digital signal layer on layer four. Place all decoupling caps as close as possible the the device as possible. Surface mount capacitors generally have lower inductance than radial lead or axial lead components. Surface mount caps should be place on the component side of the PCB to minimize inductance caused by board vias. Any vias, especially to ground, should be as large as possible to reduce their inductive effects.
Digital Interconnect
The digital inputs and outputs of the CS7654 should be isolated from the analog outputs as much as possible. Use separate signal layers whenever possible and do not route digital signals over the analog power and ground planes. Noise from the digital section is related to the digital edge rates used. Ringing, overshoot, undershoot, and ground bounce are all related to edge rate. Use lower speed logic such as HCMOS for the host port interface to reduce switching noise. For the video input ports, higher speed logic is required, but use the slowest practical edge rate to reduce noise. To reduce noise, it is important to match the source impedance, line impedance, and load impedance as much as possible. Generally, if the line length is greater than one fourth the signal edge rate, line termination is necessary. Ringing can also be reduced by damping the line with a series resistor (22-150 ). Under extreme cases, it may be advisable to use microstrip techniques to further reduce radiated switching noise if very fast edge rates (<2 ns) are used. If microstrip techniques are used, split the analog and digital ground planes and use proper RF decoupling techniques.
Power and Ground Planes
The power and ground planes need isolation gaps of at least 0.05" to minimize digital switching noise effects on the analog signals and components. A split analog/digital ground plane should be connected at one point as close as possible to the CS7654.
Power Supply Decoupling
Start by reducing power supply ripple and wiring harness inductance by placing a large (33-100 F) capacitor as close to the power entry point as possible. Use separate power planes or traces for the digital and analog sections even if they use the same supply. If necessary, further isolate the digital and analog power supplies by using ferrite beads on each supply branch followed by a low ESR capacitor.
Analog Interconnect
The CS7654 should be located as close as possible the output connectors to minimize noise pickup and reflections due to impedance mismatch. All unused analog outputs should be placed in shutdown. This reduces the total power that the CS7654 requires, and eliminates the impedance mismatch presented
53
CS7654
by an unused connector. The analog outputs should not overlay the analog power plane to maximize high frequency power supply rejection. At power up, make sure that the analog and digital supply are settled to their nominal voltage before applying any signal pin. To further prevent from external voltage anomalies a 3.3 V zener diode should be applied. The diode should be located after the filter, close to the connector. Anode connected to ground and cathode connected to the video output pin.
Analog Output Protection
To minimize the possibility of damage to the analog output sections, make sure that all video connectors are well grounded. The connector should have a good DC ground path to the analog and digital power supply grounds. If no DC (and low frequency) path is present, improperly grounded equipment can impose damaging reverse currents on the video out lines. Therefore, it is also a good idea to use output filters that are AC coupled to avoid any problems.
External DAC Output Filter
If an output filter is required, the low pass filter shown in Figure 19 can be used.
ESD and Latch up Protection
All MOS devices are sensitive to Electro Static Discharge (ESD). When manipulating these devices, proper ESD precautions are recommended to avoid performance degradation or permanent dramage. To prevent latch up, make sure that the analog ground and the digital ground are at the same potential, it also apply to the analog supply and the digital supply, they must be at the same potential.
2.2 H
IN
C1
OUT 330 pF
C2
220 pF
3.3 V
Figure 19. External Low Pass Filter C2 should be chosen so that C1 = C2 + Ccable
54
CS7654
PIN DESCRIPTIONS
SVID_Y XTAL_OUT XTAL_IN/CLKIN2X CLKOUT_GRG
SVID_C VDD_DAC GND_DAC COMP_VID
VDD_PLL GND_PLL ISET_PLL TEST1 NC NC DIN0 DIN1 DIN2 DIN3 DIN4 VDD GND DIN5 DIN6 DIN7 DIN8 DIN9 NC NC SDAM SCLM DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41
CS7654 64-pin TQFP Top View
40 39 38 37 36 35 34 33
ISET_DAC VREF VDD_BG GND_BG NC NC P4BYTMODE SCENABLE HIZEN CLKIN_GRG TEST2 RESET VDD GND VREFIN HREFIN SCLS SDAS NC NC GPIO2 GPIO1 GPIO0 CLKOUT DOUT9 DOUT8 DOUT7 DOUT6
55
CS7654
Power Supply Connection VDD - Power Supply, PINS 8, 40. Positive digital supplies. Nominally +5 volts. VDD_BG, VDD_DAC, VDD_PLL - Power Supply, PINS 50, 55, 61. Positive analog supplies. Nominally +5 volts. Respectively Bandgap, DAC and PLL supplies. GND - Digital Ground, PINS 9, 39. Digital ground supplies. GND_BG, GND_DAC, GND_PLL - Digital Ground, PINS 49, 54, 62. Digital ground supplies. Respectively Bandgap, DAC and PLL ground. Input Data and Clocks DIN[9:0] - Digital Mosaic Inputs, Pins [15:10, 7:3]. CMOS level mosaic coded CCD input data from CCD digitizer CLKIN_GRG - Mosaic Input Data Clock, PIN 43. Main system input clock, used to strobe incoming digital CCD mosaic data. The CLKIN frequency is identical to the mosaic input data rate. XTAL_IN/CLKIN2X - Mosaic Input Data Interpolation Clock, PIN 59. Mosaic input data interpolation clock or crystal oscillator input. CLKOUT_GRG - CCD Sample Clock, PIN 60. This clock is scaled by the internal PLL and is equal to the CLKIN2X frequency divided by the scaling ratio. This clock is intended to connect to the CS7615 master clock pin (pin 32). XTAL_OUT - Crystal oscillator output, PIN 58. When using the internal crystal oscillator, connect the external crystal to the XTAL_OUT and CLKIN2X pins. If unused leave floating. HREFIN - Horizontal Input Timing Reference, PIN 37. Active low horizontal input timing reference. Used to synchronize the output timing signals with the incoming mosaic data and timing. When used with CCD digitizers like the CS7615 which imbed the necessary timing signals in the data stream, the HREFIN signal is not needed. VREFIN - Vertical Input Timing Reference, PIN 38. Active low vertical input timing reference. Used to synchronize the output timing signals with the incoming mosaic data and timing. When used with CCD digitizers like the CS7615 which embed the necessary timing signals in the data stream, the VREFIN signal is not needed.
56
CS7654
I2C Serial Control SDAS - Primary I2C Data Bus, PIN 35. Primary I2C data bus. Used with SCL to read and write the internal register set. SCLS - Primary I2C Clock, PIN 36. Primary I2C Clock. Used with SDA to read and write the internal register set. SDAM - Secondary I2C Data Bus, PIN 17. Secondary I2C data bus with limited bus mastering capabilities. Used with SCLSEC to read and write I2C devices located on the secondary bus. Various devices can be isolated by the CS7654 from the primary I2C bus. The CS7654 will start reading I2C EPROM devices at addresses A0h after RESET. It will download the EPROM contents into the specified registers inside the secondary bus devices as well as any CS7654 registers specified in the EPROM entries. Devices are typically connected to either the primary or the secondary I2C bus. However, the two busses may be connected together when system design requires the use of EPROM initialization while at the same allowing direct access to all the camera devices from the external I2C controller. SCLM - Secondary I2C Clock, PIN 18. Secondary I2C clock with limited bus mastering capabilities. Used with SDASEC to read and write I2C devices located on the secondary bus. Various devices can be isolated by the CS7654 from the primary I2C bus. The CS7654 will start reading I2C EPROM devices at addresses A0h after RESET, and download the EPROM contents into the specified secondary bus registers, as well as any CS7654 registers specified in the EPROM entries. Devices are typically connected to either the primary or the secondary I2C bus. However, the two busses may be connected together when system design requires the use of EPROM initialization while at the same time allowing direct access to all the camera devices from the external I2C controller. P4BYTMODE - Four-byte Mode I2C Operation Enable, PIN 46. Places CS7654 in the Four-byte mode for I2C transactions on the primary I2C bus. Active high. Digital Video Outputs and Clocking DOUT[9:0] - Channel Digital Output Bits, Pins [28:19]. CMOS level 10-bit digital video output channel "A." Either YCrCb interleaved digital video output data, or Y component digital video data is available at this port according to the state of bit 5 in register 06h at SA 0x34h. HIZEN - Output enable, PIN 44. CMOS level digital input pin to place all digital video output in HI-Z mode. This pin works in conjunction with OE bit in register 06h at SA 0x34h. To disable/power down DAC see registers description 0x04h and 0x05h at SA 0x00h.
57
CS7654
CLKOUT - Digital Output Data Clock, PIN 29. Digital output clock. Output data transitions on the falling edge of CLKOUT and can be latched on the rising edge. The CLKOUT rate is equal to twice the input mosaic pixel rate multiplied by the current scaling ratio with Y and CrCb output data available on DOUT [9:0]. Analog VREF - External voltage reference, PIN 51. Input to an external voltage reference of 1.235V. Leave floating if unused. ISET_DAC - DAC bias, PIN 52. Connect this pin to analog ground ( AGND ) through a 4K00 Ohms 1% resistor. ISET_PLL - PLL bias, PIN 63. Connect this pin to analog ground ( AGND ) through a 6K00 Ohms 1% resistor. SVID_Y - S-Video output, LUMA , PIN 57. Current DAC output, must have a doubly terminated load of 75R0 Ohms 1% resistor. SVID_C - S-Video output, CHROMA , PIN 56. Current DAC output, must have a doubly terminated load of 75R0 Ohms 1% resistor. COMP_VID - Composite video output, PIN 53. Current DAC output, must have a doubly terminated load of 75R0 Ohms 1% resistor. Miscellaneous RESET - Master External Reset Control, PIN 41. CMOS input which initiates a complete power-on reset, where all registers are reset to their defaults, and the secondary I2C bus attempts to load any EPROM configuration information. This pin operates in conjunction with bit 0 of register 00h. RESET is an active logic low input. TEST2 - Test Pin, PIN 42. Test pin, connect to DGND. TEST1 - Test Pin, PIN 64. Test pin, connect to DGND. SCENABLE - Test Pin, PIN 45. Test pin, connect to GND.
58
CS7654
GPIO[2..0]- General Purpose I/O port, PIN [32:30]. CMOS I/O. Also use by EPROM for configuration. NC - No connect, PIN 1, 2, 15, 16, 33, 34, 47, 48. No connect, leave floating.
59
CS7654
PACKAGE DIMENSIONS
64L TQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES DIM A A1 B D D1 E E1 e L MIN 0.000 0.002 0.007 0.461 0.390 0.461 0.390 0.016 0.018 0.000 MAX 0.063 0.006 0.011 0.484 0.398 0.484 0.398 0.024 0.030 7.000 MILLIMETERS MIN MAX 0.00 1.60 0.05 0.15 0.17 0.27 11.70 12.30 9.90 10.10 11.70 12.30 9.90 10.10 0.40 0.60 0.45 0.75 0.00 7.00
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* Notes *

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